Mastodawn

Linux 6.19 Release – Main changes, Arm, RISC-V, and MIPS architectures

https://fed.brid.gy/r/https://www.cnx-software.com/2026/02/09/linux-6-19-release-main-changes-arm-risc-v-and-mips-architectures/

Linux 6.19 Release – Main changes, Arm, RISC-V, and MIPS architectures

Linus Torvalds has just released Linux 6.19 on the Linux Kernel Mailing List (LKML): No big surprises anywhere last week, so 6.19 is out as expected - just as the US prepares to come to a complete standstill later today watching the latest batch of televised commercials. The betting man would expect them all to be AI-generated, but maybe some enterprising company decides to buck the trend? Doubtful, but there's always a slight chance. But for anybody outside the US, maybe taking the newest kernel out for a spin instead is an option? I have more than three dozen pull requests for when the merge window opens tomorrow - thank you to all the early maintainers. And as people have mostly figured out, I'm getting to the point where I'm being confused by large numbers (almost running out of fingers and toes again), so the next kernel is going to

CNX Software - Embedded Systems News

eicker.news ᳇ tech news Jan 18

#KrsteAsanović, co-founder of #SiFive and a key figure in the development of #RISCV, discusses the #opensource #CPU architecture’s origins and evolution. Initially created for academic research at Berkeley, RISC-V’s modular design allowed for rapid prototyping and software development. The architecture’s openness attracted interest from both academia and industry. https://morethanmoore.substack.com/p/an-interview-with-dr-krste-asanovic?eicker.news #tech #media #news

An Interview with Dr. Krste Asanović

Putting the Drive into RISC-V

More Than Moore

N-gated Hacker News Jan 11

Ah, another brave soul attempts to shoehorn #xv6 into the almighty #SiFive HiFive Unmatched board. 🤡 Because #porting an archaic educational OS to a niche board is exactly what the world needed right now. 🙄 #GitHub, of course, stands by to witness this monumental achievement in software archaeology. 🥳
https://github.com/eyengin/xv6-riscv-unmatched #HiFiveUnmatched #softwarearchaeology #educationalOS #HackerNews #ngated

GitHub - eyengin/xv6-riscv-unmatched: A port of xv6-riscv to the SiFive HiFive Unmatched board.

A port of xv6-riscv to the SiFive HiFive Unmatched board. - eyengin/xv6-riscv-unmatched

GitHub

cnx-software.com Dec 1

Linux 6.18 release – Main changes, Arm, RISC-V, and MIPS architectures

https://web.brid.gy/r/https://www.cnx-software.com/2025/12/01/linux-6-18-release-main-changes-arm-risc-v-and-mips-architectures/

Linux 6.18 release – Main changes, Arm, RISC-V, and MIPS architectures

Linus Torvalds has just announced the release of Linux 6.18 on the Linux Kernel Mailing List (LKML), which will likely become the next LTS kernel: So I'll have to admit that I'd have been happier with slightly less bugfixing noise in this last week of the release, but while there's a few more fixes than I would hope for, there was nothing that made me feel like this needs more time to cook. So 6.18 is tagged and pushed out. Most of the last-minute fixes are minor fixes to drivers, with some random noise elsewhere (bluetooth, ceph, afs..). Nothing strikes me as standing out, but hey, there's a shortlog appended if you want to see the details. And this obviously means that the merge window will open tomorrow, and I already have three dozen pull requests pending. Thanks. And as I already mentioned a couple of weeks ago in one

CNX Software - Embedded Systems News

AS 396507 Nov 17

We've updated our tor relay build script for #RISCV, building #openssl and #tor from source:

https://code.disobey.net/EmeraldOnion/tor-openssl-riscv/

Notably, to get rid of this tor initialization warning:
> We were built to run on a 64-bit CPU, with OpenSSL 1.0.1 or later, but with a version of OpenSSL that apparently lacks accelerated support for the NIST P-224 and P-256 groups. Building openssl with such support (using the enable-ec_nistp_64_gcc_128 option when configuring it) would make ECDH much faster.

With an added openssl configure target and option:
> linux64-riscv64 enable-ec_nistp_64_gcc_128

Our #SiFive #HiFive RISC-V 256-bits ECDH performance is synthetically boosted:

From:
> 256 bits ecdh (nistp256) 0.0029s 340.7

To:
> 256 bits ecdh (nistp256) 0.0005s 2057.1

This is a 6x P-256 handshakes boost, so this should help speed up this Tor exit relay. We are only running one Tor daemon on this hardware to see how well it does.

LinuxGizmos.com Oct 15

Upbeat and SiFive Launch Ultra-Low Power RISC-V MCU with AI Acceleration

https://fed.brid.gy/r/https://linuxgizmos.com/upbeat-and-sifive-launch-ultra-low-power-risc-v-mcu-with-ai-acceleration/

ALT-F4.cz Aug 8, 2025

Kickstarterová kampaň na odlehčenou verzi VisionFive 2 spuštěna
#SiFive #RISC-V
https://alt-f4.cz/kickstarterova-kampan-na-odlehcenou-verzi-visionfive-2-spustena

Kickstarterová kampaň na odlehčenou verzi VisionFive 2 spuštěna | ALT-F4

Brad Linder Aug 7, 2025

StarFive VisionFive 2 Lite is a cheap(er) RISC-V single-board computer (crowdfunding)

The VisionFive 2 Lite is a credit card-sized single-board computer (SBC) that looks a lot like a Raspberry Pi. But it’s actually a smaller, cheaper, and less powerful version of the VisionFive 2 RISC-V SBC that launched a few years ago.

The new model has a slower version of the same processor and loses a few ports and connectors, but picks up optional support for onboard WiFi and Bluetooth. […]

#crowdfunding #riscV #sbc #sifive #starfive #starfiveVisionfive2Lite