AeroVironment décroche le P550 pour l’armée US, un drone longue portée qui change la donne sur le terrain
https://aeromorning.com/larmee-americaine-attribue-un-contrat-de-production-pour-les-systemes-de-reconnaissance-longue-portee-p550-de-la-societe-aerovironment-av/
#Space #Science #Innovation #AerospaceEngineering #MilitaryDrones #P550 #DroneTech

A #RISCV Progress Check: Benchmarking #P550 and #C910
The RISC-V cores fall short of Ar #CortexA73 and well short of Intel’s #Goldmont Plus. Mediatek’s In-Order #Genio1200 hyas higher clock speeds and better DRAM latency than C910 and P550. Its #CortexA55 cores are able to catch C910 and P550 without out-of-order execution.
#SiFive’s P550 and T-HEAD’s Xuantie C910 are both notable for featuring out-of-order execution on RISC-V. Both are plagued by low clock speeds.
https://chipsandcheese.com/p/a-risc-v-progress-check-benchmarking

Inside #SiFive’s #P550 #RISCV Microarchitecture
It doesn’t go head-on against likes of AMD’s Zen 5, Intel’s Lion Cove, or Qualcomm’s Oryon. P550’s out-of-order engine is closer in size to something like Intel’s Core 2 from over 15 yrs ago. Combine that with much lower clock speeds than even what Core 2 ran at, and P550 is really a low power core with modest performance. This core aims for “30% higher performance in less than half the area of a comparable Arm Cortex A75.”
https://chipsandcheese.com/p/inside-sifives-p550-microarchitecture

#SiFive #HiFive Premier #P550 #RISCV Price Lowered to $399, ready to go with #Ubuntu 24.04 LTS Support
This RISC-V developer board features the SiFive P550 CPU, 128GB eMMC storage, 16GB or 32GB of LPDDR5 memory, PCIe connectivity, M.2 storage support, USB 3, and more.
https://www.phoronix.com/news/HiFive-Premier-P550-Drop

#SiFive selects a faster #China-made #RISCV #CPU instead of an #Intel chip for its latest board
#HiFivePremierP550 will be first commercial out-of-order RISC-V dev board.#P550 has 16GB of LPDDR5-6400, a 128GB eMMC SSD for "fast bootable" storage. A single PCIe 3.0 x4 interface along with five USB 3.2 Gen 1 ports. The #Eswin #EIC7700 SoC features four P550 cores, 256KB of L2 cache, and 4MB of L3 cache. Superscalar P550 can issue three instructions per cycle per core.
https://www.tomshardware.com/pc-components/cpus/sifive-selects-a-faster-chinese-made-risc-v-cpu-instead-of-an-intel-chip-for-its-latest-development-board