#FOSDEM 2026 was awesome! 🧇

Very cool to meet lots of interesting people :) 🍻 🫂

Video & Slides of my talk about SucréLA are online! 🎉

SucréLA: open source usb 3.0 logic analyzer based on FPGA https://fosdem.org/2026/schedule/event/WSKHHU-sucrela_open_source_usb_3_0_logic_analyzer_based_on_fpga/

#FPGA #opensource #hardware #logiciellibre #sigrok #litex #soc #pcb #usb

Well that's kind of frustrating. This LiteDRAM DDR2 controller using sim mode (built-in DRAM model) eats the write transaction, eats the read transaction, and then never responds.

I followed the init_sequence from the generated C code, but I have a hunch more is required.

#fpga #litex

Litex: The First Formal Language Learnable in 1-2 Hours

https://github.com/litexlang/golitex

#HackerNews #Litex #Formal #Language #Learnable #Programming #Education

I'm making lots of progress on the HydraSucréLA bringup! 🎺

Open source sw/hw/gateware logic analyzer incoming!

It's already capturing 🎉 🥳

#opensource #hardware #fpga #ecp5 #LiteX

Pro tips when using Migen's SyncFIFO() module in your pipeline design...

I went from 70 MHz max frequency to 100+ MHz by just adding this parameter: `buffered=True`

It helped a lot for timing closure of the design :)

#FPGA #ECP5 #OpenSource #LiteX #Migen #SucréLA #HydraSucréLA