2進数だけがコンピューティングではない:独立研究者が3値RISCプロセッサ「5500FP」をFPGA上に実装

現代のあらゆるコンピュータは2進数(バイナリ)で動いている。CPUもメモリもストレージも、すべてが0と1の2状態を前提に設計されている。だが、論理を表現する方法はバイナリだけに限られない。3値論理(ternary […]

https://xenospectrum.com/ternary-risc-cpu-5500fp-fpga/

Revoltă în UE? Zece state europene, inclusiv România, cer revizuirea planului de energie verde al Ursulei von der Leyen Acestia califica cadrul actual al legislației drept un „risc existențial” pentru numeroase sectoare industriale cheie 👉 https://c.aparatorul.md/wapua 👈 #certificatelorETS #critic #Deciziile #energie #Europa #europene #Evoluțiilegeopolitice #existențial #frână #Industrie #PactulVerde #planului #Proiectuleuropean #prosperității #Revoltă #Risc #Rom...
https://c.aparatorul.md/wapua
New to me #RISC toys! Not #RISCV, I think this is RISC 2? I know has a pair of R12000 processors in it if that helps...
🌖 Dabao 開發板與 Baochip-1x:設計理念、時機與背景揭祕
➤ 挑戰 ARM 壟斷,以 RISC-V 與 MMU 為嵌入式系統帶來「桌機級」安全
https://www.crowdsupply.com/baochip/dabao/updates/what-it-is-why-im-doing-it-now-and-how-it-came-about
Andrew 'bunnie' Huang 在文中深入探討了其開發 Baochip-1x 晶片的初衷與技術願景。他強調,該晶片的核心亮點在於整合了記憶體管理單元(MMU),打破了傳統小型嵌入式系統因 ARM M 系列架構限制而缺乏虛擬記憶體的現狀。儘管目前晶片的部分 RTL 仍非完全開源,但 bunnie 認為,在完全開放的矽晶片生態系統成熟前,採取「部分開源」策略是推動開源硬體普及、降低對封閉架構(如 ARM)依賴的務實作法。他期盼透過此舉,讓開發者能提前建立基於開源標準的軟體應用,從而實現長期的硬體自主。
+ 終於有嵌入式晶片願意在 MMU 下功夫了!一直以來被
#開發硬體 #RISC-V #開源硬體 #系統架構
What It Is, Why I'm Doing It Now, and How It Came About

As a subscriber to the “Dabao” campaign, you’re already aware of the Baochip-1x. This update fills in the backstory of what it is, why I’m doing it now, and how it came about.

Crowd Supply
🌖 RISC-V 架構運行速度緩慢的現實挑戰
➤ 軟體移植之路:為何 RISC-V 距離成為主流架構還有一段距離?
https://marcin.juszkiewicz.com.pl/2026/03/10/risc-v-is-sloooow/
本文由資深開發者 Marcin Juszkiewicz 分享他在 Fedora Linux RISC-V 移植工作中的觀察。他詳細說明瞭為 RISC-V 平臺進行軟體打包的繁瑣過程,並透過客觀數據指出,受限於當前硬體效能(處理器核心與記憶體限制),RISC-V 的軟體編譯時間遠高於 x86 或 ARM 架構,甚至不得不關閉 LTO(連結時間優化)以縮短時程。作者強調,若要使 RISC-V 成為 Fedora 的官方架構,必須提升硬體效能至企業級伺服器標準,並建議現階段透過 QEMU 模擬器進行大規模多核心編譯來緩解開發壓力。
+ 這數據太真實了,RISC-V 要進入伺服器領域,硬體算力確實是最大的瓶頸,光靠情懷很難普及。
+ 作者提到的 QEMU 模擬編譯策略很實用,在硬
#RISC-V #Fedora Linux #編譯效能 #軟體開發
RISC-V is sloooow – Marcin Juszkiewicz

143 vs 36 minutes is far too big difference

👨‍💻 Oh, look! Another gripping tale of an #ARM #developer lamenting the glacial pace of #RISC-V 🐌 while pretending to be productive with Fedora's bug circus. 🎪 But hey, at least he got 86 pull requests in—a testament to truly pioneering 🚀 the art of waiting around! 😂
https://marcin.juszkiewicz.com.pl/2026/03/10/risc-v-is-sloooow/ #Fedora #pullrequests #productivity #HackerNews #ngated
RISC-V is sloooow – Marcin Juszkiewicz

143 vs 36 minutes is far too big difference

RISC-V is sloooow – Marcin Juszkiewicz

143 vs 36 minutes is far too big difference

🌘 RVA23 終結 RISC-V CPU 對投機式執行技術的壟斷
➤ 從「猜測預判」到「明確指令」:RISC-V 的效能架構轉型
https://semiwiki.com/ip/risc-v/367094-rva23-ends-speculations-monopoly-in-risc-v-cpus/
RVA23 規範的出現標誌著 RISC-V 處理器架構的重大轉折。過去,高效能 CPU 為了追求速度,過度依賴「投機式執行」(Speculative Execution),導致晶片在功耗、複雜度與安全性上付出沉重代價。RVA23 透過強制將「RISC-V 向量擴展」(RVV)納入標準,使顯性的平行運算成為處理器的核心能力,而非額外的加速組件。此舉讓 CPU 的向量單元能負責高效能吞吐,而純量核心則轉型為更簡單、可預測的協調者。這一轉變不僅提升了軟體開發的可預測性,更讓硬體設計者能擺脫無止境增加分支預測與緩衝區複雜度的困境,開創了更具能效比的計算新紀元。
+ 終於不再是為了那 5% 的單核效能提升而把 CPU 設計搞得極其複雜且充滿漏洞
#RISC-V #CPU 架構 #電腦運算
RVA23 Ends Speculation’s Monopoly in RISC-V CPUs - Semiwiki

RVA23 marks a turning point in how mainstream CPUs are expected to scale performance. By making the RISC-V Vector Extension (RVV) mandatory, it elevates structured, explicit parallelism to the same architectural status as scalar execution. Vectors are no longer optional accelerators bolted onto speculation-heavy cores. They are baseline capabilities that software can rely on. RVA23…

Semiwiki
🎉 Oh wow, #RVA23 has finally toppled Speculation's tyrannical reign in #RISC-V CPUs! Because nothing screams cutting-edge like an impenetrable wall of buzzwords and vendor names that no one asked for. 🙄 #GameChanger #zzzz
https://semiwiki.com/ip/risc-v/367094-rva23-ends-speculations-monopoly-in-risc-v-cpus/ #CPUs #Speculation #GameChanger #TechNews #HackerNews #ngated
RVA23 Ends Speculation’s Monopoly in RISC-V CPUs - Semiwiki

RVA23 marks a turning point in how mainstream CPUs are expected to scale performance. By making the RISC-V Vector Extension (RVV) mandatory, it elevates structured, explicit parallelism to the same architectural status as scalar execution. Vectors are no longer optional accelerators bolted onto speculation-heavy cores. They are baseline capabilities that software can rely on. RVA23…

Semiwiki
RVA23 Ends Speculation’s Monopoly in RISC-V CPUs - Semiwiki

RVA23 marks a turning point in how mainstream CPUs are expected to scale performance. By making the RISC-V Vector Extension (RVV) mandatory, it elevates structured, explicit parallelism to the same architectural status as scalar execution. Vectors are no longer optional accelerators bolted onto speculation-heavy cores. They are baseline capabilities that software can rely on. RVA23…

Semiwiki