#NXP s i.MX W93 seems to be quite nice toy.
It is ARM MPU with 2xA55 @1.7GHz plus 1x CM33 @450MHz
It has integrated 2.4GHz radio capable of #wifi6 #BT LE5.4 and 15.4 stuff (#zigbee / #thread)
Major drawback is it needs external DRAM so someone ( @olimex ? 😇 ) needs to create modules...
BTW why is no one adding some minimal amount of dram into MPUs package?
Gateworks GW16168 M.2 AI accelerator features NXP Ara240 DNPU with up to 40 eTOPS
NXP i.MX 937 cost-effective Cortex-A55/M7/M33 MPU is a drop-in replacement for NXP i.MX 95 SoC family
The 1 .4 GHz NXP i.MX 937 quad-core Cortex-A55 microprocessor (MPU) for HMI and Edge AI applications aims to fill the gap between entry-level NXP i.MX 93 SoCs and higher-end parts like the NXP i.MX 952 processor family, while offering pin-to-pin compatibility with the latter. The i.MX 937 MPU also features a dedicated 667 MHz Arm Cortex -M7 for real-time workloads and a low-power Arm Cortex-M33 core for system management tasks, supports LPDDR4x or LPDDR5 memory, integrates an Arm Mali G310 3D GPU, a VPU for 1080p H.26x video encoding and decoding, and a 2 eTOPS NXP eIQ Neutron NPU for machine learning (ML) acceleration. Since it targets HMI applications, we'll also find MIPI DSI and LVDS display interfaces, and a 4-lane MIPI CSI camera interface, plus various other I/Os. NXP i.MX 937 specifications: (highlights in bold compared to other i.MX 93 parts) CPU Up to 4x Arm Cortex-A55 cores
NXP i.MX 93W wireless MPU SiP pairs dual-core Arm Cortex-A55 processor with NXP iW610 WiFi 6, Bluetooth LE, and 805.15.4 radio
NXP i.MX 93W is the company's first integrated wireless MPU System-in-Package (SiP) and combines a dual-core Cortex-A55 processor (NXP i.MX 93) with an iW610 WiFi 6, Bluetooth LE, and 802.15.4 tri-radio into a single chip. The 14.2 x 12 mm package also includes all the external radio components needed for wireless connectivity, replacing up to 60 discrete components on the PCB. NXP says it reduces the PCB area, simplifies PCB design and regulatory approval, and speeds up time-to-market. NXP i.MX 93W specifications: CPU Dual-Core Arm Cortex-A55 at up to 1.7 GHz Arm Cortex-M33 core at 250 MHz for real-time control GPU - 2D graphics accelerator AI accelerator - Arm Ethos-U65 microNPU Memory I/F - Up to 3.7GT/s 16-bit LPDDR4/LPDDR4X with inline ECC Storage I/F - 2x SD 3.0/SDIO 3.0/eMMC 5.1 Display Interfaces MIPI DSI up to 1080p60 LVDS up to 720p60 24-bit parallel RGB Camera Interface - 2-lane MIPI CSI up
NXP TJA1410 and TJF1410 PMD transceivers enable “CAN-like” Single Pair Ethernet (SPE) connectivity
We've reported on 10BASE-T1S and 10BASE-T1L Single Pair Ethernet (SPE) chips from Microchip and Analog Devices in the past, which support Ethernet communication over a single twisted-pair cable. But those chips integrate a full Ethernet PHY or MAC-PHY inside the device. NXP takes a different approach with their TJA1410 (automotive) and TJF1410 (industrial) Physical Medium Dependent (PMD) transceivers. These new PMDs separate the analog physical layer from the digital Ethernet logic. By integrating the digital portion of the PHY into the host microcontroller or switch, the TJA1410 and TJF1410 only need to handle the essential analog functions for transmitting and receiving signals over the physical medium. They communicate with the host via a 3-pin OPEN Alliance (OA) interface. TJA1410 and TJF1410 PMD transceivers specifications: Networking - 10BASE-T1S (Compliant with IEEE 802.3cg and OPEN Alliance TC14,TC10 specifications) Host Interface - 3-pin OA interface (requires host MCU/switch with a 10BASE-T1S digital PHY)
NXP S32N79 octa-core Arm Cortex-A78E/12-core Cortex-R52 “Super-Integration Processor” targets Software-Defined Vehicles (SDV)
NXP recently introduced the S32N79 "Super-Integration" automotive processor, part of the S32N7 series, equipped with up to eight Arm Cortex-A78E application cores and twelve Arm Cortex-R52 cores for real-time processing. Building on the earlier 5 nm S32N55 16-core Cortex-R52 + 2x Lockstep Cortex-M7 automotive processor, the S32N79 automotive processor is still designed for software-defined vehicles (SDV), but its Cortex-A78E applications cores further enable features such as ADAS sensor fusion and data AI services, as well as improved vehicle gateway/processing functions. NXP S32N79 key features and specifications: CPU Up to 8x split-lock Arm Cortex-A78AE cores operating at up to 1.8 GHz Up to 12x split-lock Arm Cortex-R52 cores operating at up to 1.4 GHz RISC-V-based accelerator for networking, math, and data-intensive workloads AI accelerator - eIQ Neutron neural processing unit (NPU) for vehicle core NeuroNetwork offload Memory Up to 2x LPDDR4X/5/5X DRAM interfaces Up to 36 MB platform SRAM Storage 2x
Compact SMARC module combines Linux, AI, and vision on i.MX 8M Plus
Обзор 5 линеек процессоров для встраиваемого применения
В начале января несколько полупроводниковых компаний, среди которых Intel, AMD, NXP, Qualcomm, Renesas анонсировали свои новые линейки процессоров для встраиваемого применения и, как сейчас принято, ориентированных на решение задач связанных с ИИ.
https://habr.com/ru/articles/986286/
#Intel #AMD #Renesas #NXP #Qualcomm #EDGE #SDV #встраиваемые_системы
@23n27 But what if I told you that pub-key authentication for EV charging was initially defined in in 2020 with VDE-AR-E 2532-100, where the card proves the authenticity of the *UID* (yes, sorry!) by signing a challenge with its key-pair (signed by the manufacturer).
And NXP had the DESFire EV2-J, a compatible card, since around 2022, but only in homeopathic quantities?
And that you will have to replace MILLIONS OF CARDS and THOUSANDS OF READERS before you can enforce this?
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