Cologne Chip continues to push the FPGA ecosystem forward with support for free and open-source toolchain. By releasing a fully open-source toolchain, YosysHQ establish Cologne Chip as a leading supporter of transparent FPGA development. https://colognechip.com/programmable-logic/gatemate/toolchain/ #FPGA #OpenSource #GateMate #EDA

EDIT: as per @infosecdj note CologneChip did not release the toolchain. It is run by @yosyshq

This is the basic #Silice VGA test, somewhat of a tradition, I always start there when adding a new board. Who's new in this list ? Yes! Working on integrating the GateMate A1 evaluation board! Stay tuned for more info soon. #CologneChips #GateMate

GateMate DVI out.

1080P (1920×1080) @60 FPS on the #GateMate #FPGA using the TI TFP410.

He does 2 pixels per clock internally at ~74.25 Mhz, externally uses DDR at 148.5 MHz

https://elektronaut.tech/en/fpga/driving-full-hd-video-with-the-cologne-chip-gatemate-fpga/

Driving Full-HD Video with the Cologne Chip GateMate FPGA – Elektronaut

@xcabal05
I am interested in #LibreRouter technology.

The European made #GateMate #FPGA has a #5Gbps #Serdes. I can use it to do #UDP #camera in and display out. So I am just learning about the internet protocol, starting with voltages.

Which Open Source UDP library should I be using? is there one you recommend in Verilog?

There is now a github repository to compare the performance of FPGAs. The repository contains test cases for adders, counters and muxes. Now we know how much faster GateMate is than ICE40.

https://wiki.pythonlinks.info/comparing-fpgas-performance

#fpga #Lattice #ICE40 #GateMate

Comparing FPGAs' Performance

There is now a github repository to comare the performance of FPGAs.

Fully #freesoftware based support for GateMate FPGAs from Cologne Chip [0] just landed in #guix.

It includes #yosys for synthesis, #openFPGALoader for device flashing and #nextpnr for placement and routing.

guix shell -C -m manifest.scm -- make

The whole toolchain runs in a #sourcehut #ci pipeline.

https://builds.sr.ht/~csantosb/job/1588460#task-test

[0] https://indico.cern.ch/event/1587509 for details on #gatemate #fpga.

https://indico.cern.ch/event/1587509/#3-introduction

Today the #CERN 's #FPGA Developer Forum will host a seminar by Patrick Urban from #CologneChip with the title " #GateMate : a #European 28nm FPGA with an #OpenSource toolchain and radiation qualification results". The event will start at 4pm CET, there is a zoom link to follow from the remote!

[FDF Seminar] GateMate: A European 28nm FPGA with an Open-Source Toolchain and Radiation Qualification Results

Indico
Thank you @BalCCon it was again amazing experiences to be part of this super cool conference! This year I have talked about new #ULX5M board that is hosting #EU #CologneChip #GateMate chip, held small talk about #RadionaORG #ZigZag badge and had #Assembly where it was possible to assemble personalized badge!
As I did not post for a long time I will start from an end. We got #ULX5M-GS up and running!!! #CM5 pin compatible #FPGA #SoM with #EU Cologne #GateMate A1 and fully open source toolchain. Still lots of work left, but I am really happy to see DVI out!

Uhhh nice #aisler can source components without requiring that you use them for assembly.

Might be a way to share the cost of having VAT declared and also the shipping from lcsc.com.

Lets create a small test "blinkenlichts" board for my #gatemate, I could use one anyway.

They can't find the
FH-00088 (stock 920) oh well, DS1023-2*10SF11 will do just fine. Hey the system found those... claims they are not in stock (1715)?

Worse still LEDs and resistors €87, just nope, not going to happen!