GateMate DVI out.

1080P (1920×1080) @60 FPS on the #GateMate #FPGA using the TI TFP410.

He does 2 pixels per clock internally at ~74.25 Mhz, externally uses DDR at 148.5 MHz

https://elektronaut.tech/en/fpga/driving-full-hd-video-with-the-cologne-chip-gatemate-fpga/

@xcabal05
I am interested in #LibreRouter technology.

The European made #GateMate #FPGA has a #5Gbps #Serdes. I can use it to do #UDP #camera in and display out. So I am just learning about the internet protocol, starting with voltages.

Which Open Source UDP library should I be using? is there one you recommend in Verilog?

There is now a github repository to compare the performance of FPGAs. The repository contains test cases for adders, counters and muxes. Now we know how much faster GateMate is than ICE40.

https://wiki.pythonlinks.info/comparing-fpgas-performance

#fpga #Lattice #ICE40 #GateMate

Fully #freesoftware based support for GateMate FPGAs from Cologne Chip [0] just landed in #guix.

It includes #yosys for synthesis, #openFPGALoader for device flashing and #nextpnr for placement and routing.

guix shell -C -m manifest.scm -- make

The whole toolchain runs in a #sourcehut #ci pipeline.

https://builds.sr.ht/~csantosb/job/1588460#task-test

[0] https://indico.cern.ch/event/1587509 for details on #gatemate #fpga.

https://indico.cern.ch/event/1587509/#3-introduction

Today the #CERN 's #FPGA Developer Forum will host a seminar by Patrick Urban from #CologneChip with the title " #GateMate : a #European 28nm FPGA with an #OpenSource toolchain and radiation qualification results". The event will start at 4pm CET, there is a zoom link to follow from the remote!

Uhhh nice #aisler can source components without requiring that you use them for assembly.

Might be a way to share the cost of having VAT declared and also the shipping from lcsc.com.

Lets create a small test "blinkenlichts" board for my #gatemate, I could use one anyway.

They can't find the
FH-00088 (stock 920) oh well, DS1023-2*10SF11 will do just fine. Hey the system found those... claims they are not in stock (1715)?

Worse still LEDs and resistors €87, just nope, not going to happen!

Happiness is a git pull and rebuild of #nextpnr / #prjpeppercorn

Not only does "placer2" now work for me (it is a lot faster than "placer1")

But best of all my #gatemate memory mapped SPI interface now works!

"Wiggle your SPI lines in excitement" as a space invader would say.

Thanks to everyone and according to git logs for prjpeppercorn, a special thanks to Miodrag Milanovic

I give up! (for now)

Does the Masterdon network know why I can't control any of the SPI configuration flash pins on my #olimex #gatemate evaluation board?

From the .ccf file:
Pin_out "spiClk" Loc = "IO_WA_B8";
Pin_out "spiCs" Loc = "IO_WA_A8";
Pin_out "spiMosi" Loc = "IO_WA_B7";
Pin_in "spiMiso" Loc = "IO_WA_A7";

And the synth log indicates that yosys mapped the correct primitives to the pins

Mapping port top.spiClk using CC_OBUF.
Mapping port top.spiMiso using CC_IBUF.