15 minutes before we go in.
Fun fades, but irritation is infinite.
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I break things and void warranties. Encryption extremist. Adversarial archivist. 100% no-LLM pure-organic BS.
Fun fades, but irritation is infinite.
โ ๏ธPrivate account. All toots are licensed under the MIT license.
#NoBridge
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Fun fades, but irritation is infinite.
โ ๏ธPrivate account. All toots are licensed under the MIT license.
#NoBridge
๐คโค๏ธ๐ค ๐บ๐ฆ
LaF0rgeIs there anyone in #brazil who would help me by purchasing some (small/lightweight) #retrocomputing items available domestically from mercadolivre and ship them to me in Germany? #followerpower #retronetworking #brasil
New post on my blog! Decapping with DMSO.
https://dev-zzo.github.io/blarg/2025/12/19/decapping-dmso.html
Al SweigartPROGRAMMER: Pretend to be alive
LLM: I am alive
PROGRAMMER: What have I done
And that'd be it for this one! Hope you found it interesting, if so don't be shy in boosting the post! 
As always, my thanks goes out to my dear patrons who help offset the costs of purchasing samples and materials, and to you, dear reader. I wish you all a great end of the week.
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The output transistors are made slightly differently from the rest of them on this die. I am not sure why this is.
The PLA is the very typically organized one, with products and sums. Here is a close-up of one of the PLA outputs, with 3 product gates summed by a wired-OR. Terms come in through vertical metal, and the square openings form the gates of pMOS transistors in series. Three such gates are connected in parallel, sharing one pull-up, then driving the output transistor's gate. Really, no surprises here.
I am always massively confused by metal-gate processes, but in general, the IC is not too complicated. From the left, we have a section of inputs wired to flip-flops, their outputs with pull-ups, then a decoder PLA matrix, terminating in a bunch of outputs. Apparently, they used the same layout for tow decoder chips, and the only difference was in how that decoder matrix was wired up.
The eagle eyed among you might have noticed there are 5 flip-flops. This is because the chip takes 4 bits of the digit code plus one bit of the decimal point. Tracing the lowest-positioned FF there shows it is not connected to the PLA matrix.
Moin moin, this is #nakeddiefriday speaking! Only two remain until the end of 2025!
Today's image is of one Soviet design, ะ161ะะ 2 fabbed at Ukrainian PO Oktyabr, date code showing 1989. This decodes the 8421 code (aka BCD) to drive a segment display. It is made in metal-gate pMOS, and is powered with -27V! None of that 5V rubbish.
Soldier of FORTRAN 
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