Hello and welcome to the #nakeddiefriday again. This one will be a continuation of the previous one with the same exhibit but in more depth. :-)

To remind you, this is the unnamed smartcard IC, which I believe was fabbed by Samsung.

Let's try removing some metal from the top. ๐Ÿงต

#electronics #reverseengineering #smartcard

Interestingly, the thick infill area was way more resistant to the lapping process and the majority of metal-3 remained there, while the rest got stripped off.

There is a lot of analog circuitry on the bottom and right sides of the chip. I am not sure why there is so much and what it does exactly.

A detail view on the analog section; the features on the right seem to be four resistor arrays of the same value, and those on the left are multiple capacitors connected in parallel. I wonder why they decided to make multiple separate parts instead of making a large one of required geometry.
A detail view of the sea of gates. Note the difference in the shade of blue.
The smaller memory array in bottom left is certainly an SRAM block.
@infosecdj What node is this? You're getting beautifully sharp optical images indicating it's nowhere near at the limits of optical resolution, yet it's also multiple metal layers, standard cell based, planarized, etc. That's not a combo I see too often.
@azonenberg If only I knew. This certainly seems to be on the larger side, as everything is very well resolved indeed, at least on metal layers. Poly might get close to the limits of at least my system, the ROM is challenging to resolve well.
@infosecdj it feels like 350 give or take a node
@azonenberg I measured the metal-1 wire width, which came in about 677nm. Poly wiring looks about the same width. Again, a large margin of error as it is only about 13 pixels wide and the setup is not perfectly calibrated.

@infosecdj So could be a 500ish nm class node then. That would make sense, I've seen one 500nm node (on the FT232R) that was planarized.

Usually once you go much larger it's non-planar though