✧✦Catherine✦✧
the previous time i was drawing a meme about Octal SPI (below), Hexadeca SPI did not exist yet. that one is a certified 2024 moment
we did, indeed, go wider
Andrew Zonenberg@whitequark Coming soon to a memory vendor near you: 32 bit DDR SPI with four 8-bit byte groups and separate DQS for each, using SSTL signaling because LVCMOS didn't scale well.
@whitequark And after that? Back to the serial roots. Where "serial" means 1-16 8b10b coded bonded differential pairs.
@whitequark In all seriousness I've been dreaming for years of a PSRAM with integrated controller that had a SERDES interface.
Imaging being able to hang a GB of RAM off your FPGA/SoC using a single GTX lane, or add more lanes if you need more bandwidth.
@azonenberg I wonder how much worse the latency would get...
@whitequark The extreme of my vision (possibly not doable without more power pins) was an 8 pin DFN package like QSPI flash.
Left side: Vdd - TXP - TXN - Vss
Right side: Vdd - RXP - RXN - Vss
@azonenberg no reference clock? that sounds like you'd have standby power issues
@whitequark Yeah you'd probably want some GPIOs for power down and refclk at minimum. That was more of a pipe dream than practical (although IIRC SD Express doesn't use refclk so idk)
@azonenberg given the primary application (high resolution digital cameras), race-to-idle isn't really on your list of concerns
@whitequark Yeah. But my intended use case is also not things that spend a lot of time in standby either.
This kinda ties into - and perhaps could even use the same protocol as - my dream of a "pcie lite" protocol that only supports point to point operation and no plug-and-play. Just a fixed range of address space mapped over a single lane serial link.
Basically AXI fed into a SERDES.
And I want this as standard on high end MCUs (STM32H7 / RA8M1 / I.MX RT class).
Vincent Baeten@azonenberg @whitequark Begins to sound like the Xilinx aurora protocol
@vbaeten @whitequark Show me a cortex-m7 or m85 with an aurora peripheral and I'll buy it.
SnowFox@azonenberg @whitequark If you don't need the duplicate Vdd/Vss then you have two pins free!
@whitequark Basically I want hybrid memory cube scaled down to the hyperram size/cost range.
Ignas Kiela@azonenberg @whitequark There is that Open Memory Interface that newer POWER systems use, but OpenCAPI which managed that got merged into CXL and it seems like OMI got kinda left behind
There is a Microchip DDR4 controller with 8x25G channels, which is maybe a bit too thick for what you're looking for, but I guess Microchip will keep making them as long as IBM will keep making POWER 9 (quite a while I'd guess)
https://ww1.microchip.com/downloads/en/devicedoc/00003152b.pdf
There is a Microchip DDR4 controller with 8x25G channels, which is maybe a bit too thick for what you're looking for, but I guess Microchip will keep making them as long as IBM will keep making POWER 9 (quite a while I'd guess)
https://ww1.microchip.com/downloads/en/devicedoc/00003152b.pdf
@azonenberg CXL: am I a joke to you?
@ignaloidas @whitequark I'm fine with 128/130 or 64/66, not picky about line coding.
But CXL is overly complex for this use case I think.
@ignaloidas @whitequark (and I'm targeting lower end/lower cost FPGA/MCU use case so e.g. 5/10G SERDES not 32G)
@ignaloidas @azonenberg afaik CXL does actually drop to lower rates, it just can't maintain the latency guarantees
@whitequark @ignaloidas I mean whether mandated by spec or not I expect most implementations would, since it's just PCIe PHY right? Almost certainly using bog-standard PCIe IPs.
@azonenberg @ignaloidas it is a PCIe physical PHY and logical PHY, with some additional packet types that go in between the usual TLPs
@azonenberg @ignaloidas (I haven't personally worked with it but my headmate has studied it for $PAST_WORKPLACE and I looked over her shoulder while she did it)
@whitequark I was just about to say something about DQS then saw you had it in there already.
Are you looking at hyperram or STM32H7 OCTOSPI?
cynicalsecurity 
@whitequark did I miss the memo which uncursed DDR?
rat (mibioctet)@whitequark @domi showing my therapist this image
Therapist: 16 bit SPI isn't real and can't hurt you
Richard Hendricks@whitequark *shrieks, throws phone on the ground*
AMS@whitequark Having made 50MHz QSPI work over ~150mm of wirewrap in a bed of nails tester where none of the pins were anywhere close to each other I weep every time I see another half-baked spi derived mess.
@AMS that's incredibly impressive
@whitequark I'm more impressed they had it working at all before the wires were length matched and tied down. Apparently shaking the fixture was enough to wiggle the breakout board that was just hanging in there to go from working to not.