✧✦Catherine✦✧
the previous time i was drawing a meme about Octal SPI (below), Hexadeca SPI did not exist yet. that one is a certified 2024 moment
we did, indeed, go wider
Andrew Zonenberg@whitequark Coming soon to a memory vendor near you: 32 bit DDR SPI with four 8-bit byte groups and separate DQS for each, using SSTL signaling because LVCMOS didn't scale well.
@whitequark And after that? Back to the serial roots. Where "serial" means 1-16 8b10b coded bonded differential pairs.
@azonenberg CXL: am I a joke to you?
Ignas Kiela@ignaloidas @whitequark I'm fine with 128/130 or 64/66, not picky about line coding.
But CXL is overly complex for this use case I think.
@ignaloidas @whitequark (and I'm targeting lower end/lower cost FPGA/MCU use case so e.g. 5/10G SERDES not 32G)
@ignaloidas @azonenberg afaik CXL does actually drop to lower rates, it just can't maintain the latency guarantees
@whitequark @ignaloidas I mean whether mandated by spec or not I expect most implementations would, since it's just PCIe PHY right? Almost certainly using bog-standard PCIe IPs.
@azonenberg @ignaloidas it is a PCIe physical PHY and logical PHY, with some additional packet types that go in between the usual TLPs
@azonenberg @ignaloidas (I haven't personally worked with it but my headmate has studied it for $PAST_WORKPLACE and I looked over her shoulder while she did it)