✧✦Catherine✦✧
the previous time i was drawing a meme about Octal SPI (below), Hexadeca SPI did not exist yet. that one is a certified 2024 moment
we did, indeed, go wider
Andrew Zonenberg@whitequark Coming soon to a memory vendor near you: 32 bit DDR SPI with four 8-bit byte groups and separate DQS for each, using SSTL signaling because LVCMOS didn't scale well.
@whitequark And after that? Back to the serial roots. Where "serial" means 1-16 8b10b coded bonded differential pairs.
@whitequark In all seriousness I've been dreaming for years of a PSRAM with integrated controller that had a SERDES interface.
Imaging being able to hang a GB of RAM off your FPGA/SoC using a single GTX lane, or add more lanes if you need more bandwidth.
Ignas Kiela@azonenberg @whitequark There is that Open Memory Interface that newer POWER systems use, but OpenCAPI which managed that got merged into CXL and it seems like OMI got kinda left behind
There is a Microchip DDR4 controller with 8x25G channels, which is maybe a bit too thick for what you're looking for, but I guess Microchip will keep making them as long as IBM will keep making POWER 9 (quite a while I'd guess)
https://ww1.microchip.com/downloads/en/devicedoc/00003152b.pdf
There is a Microchip DDR4 controller with 8x25G channels, which is maybe a bit too thick for what you're looking for, but I guess Microchip will keep making them as long as IBM will keep making POWER 9 (quite a while I'd guess)
https://ww1.microchip.com/downloads/en/devicedoc/00003152b.pdf