✧✦Catherine✦✧
the previous time i was drawing a meme about Octal SPI (below), Hexadeca SPI did not exist yet. that one is a certified 2024 moment
we did, indeed, go wider
Andrew Zonenberg@whitequark Coming soon to a memory vendor near you: 32 bit DDR SPI with four 8-bit byte groups and separate DQS for each, using SSTL signaling because LVCMOS didn't scale well.
@whitequark And after that? Back to the serial roots. Where "serial" means 1-16 8b10b coded bonded differential pairs.
@whitequark In all seriousness I've been dreaming for years of a PSRAM with integrated controller that had a SERDES interface.
Imaging being able to hang a GB of RAM off your FPGA/SoC using a single GTX lane, or add more lanes if you need more bandwidth.
@whitequark The extreme of my vision (possibly not doable without more power pins) was an 8 pin DFN package like QSPI flash.
Left side: Vdd - TXP - TXN - Vss
Right side: Vdd - RXP - RXN - Vss
@azonenberg no reference clock? that sounds like you'd have standby power issues
@whitequark Yeah you'd probably want some GPIOs for power down and refclk at minimum. That was more of a pipe dream than practical (although IIRC SD Express doesn't use refclk so idk)
SnowFox@azonenberg @whitequark If you don't need the duplicate Vdd/Vss then you have two pins free!