#introduction #reintroduction for all the new folks around here I'm hearing about.

I'm an experimental particle physicist working on the CMS experiment. My primary foci at the moment are top quark physics through the lens of EFT (effective field theory), and FPGA programming for the purpose of development, testing, and operations of detector electronics.

Before CMS, I worked on the SuperCDMS experiment looking for dark matter. I developed the level 1 trigger for the upcoming SuperCDMS run at SNOLAB, and also developed the simulation of the transition edge sensors and charge sensors that are part of the SuperCDMS detectors.

Before SuperCDMS, I worked on the CDF (Collider Detector at Fermilab) experiment. There, I studied the top quark and the Higgs boson. I performed the world's first-ever published search for ttH production, and measured the forward-backward asymmetry in top-antitop production at the Tevatron.

#topquark #EFT #fpga #electronics #darkmatter #simulations #detectors #Higgs #Higgsboson #CMS #CERN #LHC #Tevatron #CDF #Fermilab #darkmatter #SuperCDMS #SNOLAB

@jswphysics
Greetings! I worked at Fermi a long way back a couple summers with the experimental astrophysics group doing the Sloan digital sky survey. I now do #fpga in a very different field of wireless modems for live sound. I have fond memories of the science world.
@jswphysics
So what will your current #fpga project actually do? Do you have a link?

@PythonLinks
In roughly 2026, the "high luminosity" run of the LHC will begin. To cope with both the increased data rates and increased radiation, some parts of the CMS detector will be replaced. Among those is the endcap calorimeter.

The new endcap calorimeter includes new electronics. Because it has to operate in both a high radiation environment and a high magnetic field, we cannot use off the shelf components. Also, some of what we need to do is so specialized that no off the shelf component would do it. So, a few different institutions are designing new ASICs for the endcap calorimeter upgrade.

I write and support firmware for doing QC and QA testing of the electronics, both individual ASICs and systems integration tests. Part of this involves taking the ASIC designs and adapting the RTL code to an FPGA, so that we can emulate the ASICs in system tests before they actually become available.