Riley S. FaelanBecause of historic compatibility reasons, I sort of ended up rewriting a subset of #Microblaze-compatible core for synthesising on tight corners inside Lattice's ICE40/ECP5 #FPGA:s.
It's in #Verilog with some #LiterateProgramming preprocessing. Userspace (and I/O+interrupt support) only. Explicit support for combining code and data bus, optionally for 8-bit memory access (as in HyperRAM), or for synthesising instruction memory as block RAM, optionally with a secondary debug interface. Explicit support for resetting the core without resetting the whole FPGA. AXI-like, Wishbone-compliant, and serial I/O support, and I/O-mappable interrupt support. The register file can be pared down. Arithmetics can be divided up into chunks of a parametrically specified size, all the way down to bit-serial if need be, and slow-but-smol microcoded multiplication and division are optionally available. Some optional extensions for fixed-point transcendental calculations were originally planned, but right now, only binary logarithms and CORDIC are ready.
The original commercial interest in it is likely to go away in the near future. Would there be interest in a GPL release of this sort of thing?
This is not at all the sort of context that MicroBlaze was originally designed for, even in the Xilinx world, and I'm not sure that the specific backwards compatibility reasons exist outside this particular niche (=> I would probably not be doing maintenance work on the core after release without a good $€parate r€a$on), but if you have a use case that might match something like these criteria, please let me know.
(Obligatory LBNL: only deterministic automation was used in writing this code. GenAI has not touched any part of it.)
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