roukemap

@[email protected]
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23 Following
107 Posts
FPGA Designer by Day
Interested in all things low-level tech by night
Show threadroukemapMar 13

@azonenberg
Tied an (unused) FPGA bank VCCO to ground and it really wanted go to a power on this device. 0.8mm bga two vcco pins per bank. Found an alternative workaround with no mods in real life, but I think I was showing our techs on of your blog posts at one point.

Two ldos, one got copied from the other in schematic, and the vset and ilim net labels didn't get renamed. Just needed some surface cuts to split the nets.

Show threadroukemapMar 1
@0xC01DC0FFEE @whitequark @azonenberg The storage layers don't need any individual patterning by photolithography, just careful thickness control in the deposition. There's some other tricky bits, but that's one of the big wins.
Show threadroukemapFeb 28
@whitequark interesting to think about the order of operations. How many dies do they stack before the first wire bonding pass. 4? 5? Do they trust placing a die right beside the freshly made wire bonds?
roukemapFeb 28
✧✦Catherine✦✧Feb 28
I would like to formally announce that the #GlasgowInterfaceExplorer revD development (the next iteration: with the same FPGA but 32 digital I/Os and 8 single-ended analog channels that can be configured as 4 differential ones) is well underway with a CrowdSupply campaign planned later this year; stay tuned!
Show threadroukemapFeb 28
@whitequark /pokes 2048 mbit ospi flash on the board I'm currently bringing up with a stick
roukemapFeb 26
✧✦Catherine✦✧Feb 26
#GlasgowInterfaceExplorer now has (or about to have) a first-class progress bar implementation with a nice API that takes into account terminal writes elsewhere in the Python application as well as nested or concurrent progress trackers resulting from applet composition!
Show threadroukemapFeb 18
@craigjb Add a layer of abstraction and expose your custom (FPGA based) device over NVMe! Now it can be used over PCIe directly, over USB and over the network (NVMe over fabrics). USB would be a bit of a pain since there is a full protocol translation to USB Mass Storage. At least NVMeoF is a bit more transparent.
Show threadroukemapFeb 4
@dlharmon XP5IO can do fast LVDS still AFAIK (I think the presentation even says it's faster than HPIO at 1800mbps vs 1600). Do lose the ability to do PCIe x16 I believe (but get gen4 in exchange).
roukemapJan 19
hackadayJan 19

SoundSlab: How to Make a Synthesizer With All the Button Screens

https://hackaday.com/2026/01/19/soundslab-how-to-make-a-synthesizer-with-all-the-button-screens/

SoundSlab: How To Make A Synthesizer With All The Button Screens

Although arguably redundant on a typical computer keyboard, the idea of embedding small screens into the buttons on devices like audio production gear that often have so many buttons can make a lot…

Hackaday
Show threadroukemapDec 22
@azonenberg @dlharmon @tom_verbeure @craigjb
When the DRP started appearing, Xilinx was more in the IBM camp. Virtex 4/5 with PowerPC hard cores. PLB and OPB interconnects instead of AMBA. You can still see the legacy in the Microblaze ISA spec, which uses IBM bit numbering (I'm not bitter), but I guess that's finally going away since I expect the RISC-V Microblaze is replacing the proprietary one eventually.