roukemap
✧✦Catherine✦✧I would like to formally announce that the #GlasgowInterfaceExplorer revD development (the next iteration: with the same FPGA but 32 digital I/Os and 8 single-ended analog channels that can be configured as 4 differential ones) is well underway with a CrowdSupply campaign planned later this year; stay tuned!
jeeger
Viola@whitequark That's very exciting, looking forward to it :3 ! I know it's a long shot, but I was wandering if usb3 SS could be possible (maybe with the new chips from wch or the FX3) instead of the usb2 interface.
@viola eventually yes but not for revD0 (or the CS campaign), the overall design and schematic are essentially finalized
@viola there are multiple issues with 3 Gbps plus data transfer rates, not the least of which is that Python will struggle to meaningfully process anything at that speed
@whitequark I see, that's understandable. Still awsome, I'll definately get one
jn (big endian energy)@whitequark is it planned to have Ethernet as the host interface?
@jn not for revD, but for revE yes
@whitequark rev "E for Ethernet" :)
@jn exactly
balletproof vest@whitequark will the logic analyzer be back for that?
@nyankat yes; the LA needs bigger on-board memory than the 16 KB the FPGA has, which in turn needs HyperRAM (revC, as an addon) or Octal SPI RAM (revD); once the memory controller is ready, existing revC devices could be upgraded with an addon that mates with the board inside the case, and all revD devices will have it as standard
@whitequark thanks!
@nyankat main thing the memory controller is/was blocked on was the lack of a sound design methodology for designing complex serial I/O interfaces in Amaranth, but I came up with it in the last 1-2 years so that's now ok