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FPGA Designer by Day
Interested in all things low-level tech by night
I would like to formally announce that the #GlasgowInterfaceExplorer revD development (the next iteration: with the same FPGA but 32 digital I/Os and 8 single-ended analog channels that can be configured as 4 differential ones) is well underway with a CrowdSupply campaign planned later this year; stay tuned!
#GlasgowInterfaceExplorer now has (or about to have) a first-class progress bar implementation with a nice API that takes into account terminal writes elsewhere in the Python application as well as nested or concurrent progress trackers resulting from applet composition!

SoundSlab: How to Make a Synthesizer With All the Button Screens

https://hackaday.com/2026/01/19/soundslab-how-to-make-a-synthesizer-with-all-the-button-screens/

SoundSlab: How To Make A Synthesizer With All The Button Screens

Although arguably redundant on a typical computer keyboard, the idea of embedding small screens into the buttons on devices like audio production gear that often have so many buttons can make a lot…

Hackaday
We’re still waiting for YOUR submission!! https://forms.gle/kDGTVqfVAZXmPoph8

I'm trying to compile some relatively simple C software from 2006. This wouldn't normally be an issue, but... it's using SCons.

SCons uses Python.

Python has gone through some major changes since then: there's Python 3.x, of course, but SCons 0.96 also relies on "as" not being a reserved word, so it's actually broken at Python 2.5.

So even cobbling together a "Python 2" install hasn't sufficed, because that got me 2.7.

I'm about ten minutes from handwriting a makefile. Make is hot garbage but at least it doesn't have this specific problem.

@projectgus this is why Amaranth has a blanket "no AI" contribution policy: you could argue about its social-scale problems but my view is that it fades in comparison to "if I have to deal with slop being submitted I will simply choose to not take submissions from an open set of people at all"

"no AI PRs" is a compromise, with the other option being "the only way to get your code in is to be from the same guild"

Day 6: brought up software execution on both cores from internal RAM. Wrote audio output pipeline for the APU. The orange/red here is the clock tree insertion for the audio clock domain; I might have over-egged it with the filter taps. Also APU has full RV32I register file now.
They should invent a statically typed Python so I don't have to do a million cycles of HDL sim before the interpreter tells me I called a function with the wrong number of arguments

I have to get to work now, first call of the day is in 3 minutes.

But this is good data so far. I've pretty much ruled out at least this sample being an outright fake.

I think this is about as much as I can do with the sample in package since I don't have any NIR / laser / probing capabilities at home.

After work, my plan is to toss it back in the acid with no mask and fully remove the remainder of the package, preserving the leadframe. Ideally I'll end up with a bare die on a copper paddle with 48 little solder lands dangling off bond wires.

If I don't see anything obviously fishy in the bond wires I'll pluck them, then clean the die surface more thoroughly and get some high-res images of the surface and see how it looks.

I'll keep the paddle intact for now both for easier handling (less risk of scratching the silicon if I'm not touching it directly) and to hold the die together in case it's got a hairline fracture I haven't seen yet.

I can easily remove it with hydrochloric or nitric acid in the future if I judge it necessary.

Does anyone have good reading material or experience to share regarding credit-based flow control systems, strategies for designing effective ones, etc?

I'm trying to maintain high throughput across a link with an unknown latency that could range from microseconds to hundreds of milliseconds, while not adding excessive additional latency due to buffer bloat.