I committed to taping out RISCBoy on GF180MCU. Will re-use a lot of the existing RTL, but the main processor will be Hazard3 and probably a second (smol) instance for the audio processor. Two weeks to deliver the final GDS. I may regret this but let's go 🥳
Thank you very much @mole99 for offering me a slot on the first https://wafer.space shuttle!
wafer.space - Budget silicon manufacturing.

Create integrated circuits without breaking the bank!

Day 1: we have a GDS with 8 kB of RAM, a Hazard3 and JTAG.
I cannot condone globbing for magic cell names in constraints. BUT, that doesn't mean I don't do it

Flop: 63.7 squm
Mux: 28.5 squm
Scan flop (forbidden fruit): 83.4 squm

You know what this means gamers

https://gf180mcu-pdk.readthedocs.io/en/latest/digital/standard_cells/gf180mcu_fd_sc_mcu7t5v0/cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq_1.html

gf180mcu_fd_sc_mcu7t5v0__sdffq_1 — GlobalFoundries GF180MCU PDK 0.0.0-111-gde3240d documentation

Also seems like there are no DFFEs in the library. At least mapping those to scan flops with Q connected to SI would save some area, routing and (I think) datapath delay.

@lofty pointed me to the USE_LIGHTER flag too, which can infer clock gates from DFFE groups.

Really this is stuff to look into when I have a bit more RTL in place, but I'm a bit alarmed by the QoR I'm seeing.

Somehow wherever I go I can't escape from YAML
First time I have really used cocotb. It's ok but the documentation of the force/release model was absolutely shocking. Took me a while to figure out how to stop driving a bidirectional pin. Anyway here is some Python bitbanging some RISC-V debug over my home-made debug transport
I found a bug in the APB crossing from the Hazard3 JTAG DTM, *if* you instantiate it outside of the JTAG DTM and use it for regular APB. I'm using it for a bus CDC between the TWD-DTM and the Debug Module.

I should be able to bring up a lot of basic tests by just poking things through the debug, so this saves me writing any software yet.

When I get to it I'm going to use a sea-of-gates ROM (~100 bytes) for the bootloader, which will just checksum 8 kB of data from SPI flash into internal RAM and jump straight in

Lost a bit of precious time to debugging the fact that, if you have a cocotb test that forgets the boilerplate to start the clock, cocotb will block forever as iverilog simulates to time infinity, and you get an empty waveform dump. Every tool has foibles I guess
They should invent a statically typed Python so I don't have to do a million cycles of HDL sim before the interpreter tells me I called a function with the wrong number of arguments
@wren6991 My blurry eyes read “Statistically typed Python” and I pondered the concept…
@tommythorn @wren6991 def fn(a: 50%int | 50%float, b: 25% float | 25% int |50% string) -> 25% float | 25% int | 50% TypeError:
a + b

@thezoq2 @tommythorn @wren6991 Isn't this kind of what Tinymist is doing for Typst?

https://myriad-dreamin.github.io/tinymist/

Introduction - Tinymist Docs

Tinymist [ˈtaɪni mɪst] is an integrated language service for Typst [taɪpst]. You can also call it 微wēi霭ǎi in Chinese. It contains: an analyzing library for Typst, see tinymist-query. a CLI for Typst, see tinymist. which provides a language server for Typst, see . which provides a preview server for Typst, see . a VSCode extension for Typst, see Tinymist VSCode Extension. Features Language service (LSP) features: Semantic highlighting The "semantic highlighting" is supplementary to "syntax h...

@wren6991 Maybe the answer is to not use Python…
I began purging scripts (bash and python especially) from my life, rewriting them as cargo-scripts