Gray Beard1d ago

SystemLisp - an HDL simulator written in Common Lisp

https://github.com/systemlisp

#lisp #commonlisp #hdl #rtl #verilog #design #verification #vhdl #systemverilog #vlsi #programming #fpga

systemlisp - Overview

An experimental HDL simulator written in Common Lisp focused on interactive and extensible hardware design and verification. - systemlisp

GitHub
Show threadPaolo Amoroso

@jackdaniel may be interested in this as it also runs on ECL.

@graybeard85

Mar 27 at 8:18pmWeb
Show threadGray Beard21h ago
@amoroso @jackdaniel Give it a try and let me know what you think. Report any issues on GitHub.