Over the weekend I worked on 🏝️Isle.Computer designs for chapter 6. I've now added the designs to a branch and you can already run the sim on your PC (Linux/Mac/Windows): https://github.com/projf/isle/tree/ch06-input-output/boards/verilator
Please have a quick play and let me know how you get on. 🛝
Chapter 6 features the FemtoRV "electron" RISC-V CPU. This CPU can multiply and divide all by itself! That comes in handy when converting integers to and from strings, amongst other things.
I've also got a whole blog post on the #riscv mul and div instructions: https://projectf.io/posts/riscv-multiply-divide/
Integer multiply and divide instructions form the optional M extension. Making multiplication and division optional keeps the base instruction set simple and reduces the size of the smallest RISC-V core. This post includes a brief overview of common RISC-V extensions.
If you enjoy my work on 🏝️ Isle.Computer, FPGAs, and RISC-V, consider sponsoring me: https://projectf.io/sponsor/
You get early access to source code and blog posts, and I send you a newsletter every month or so. Plus, you help me bring these open-source projects to life. ☺️
I‘ve upgraded 🏝️ Isle with the FemtoRV32 "Gracilis" CPU (RV32IMC); it even has interrupt support, which we’ll make use of later. 😄
I’ll release the next Isle chapter soon, with keyboard input and the start of our #RISCV software library. There’s simulation with graphics for Linux/Mac/Windows too.
I always think the next chapter of 🏝️ Isle.Computer will be smaller and done sooner, but it never is. 😅
96 changed files with 6,169 additions and 538 deletions.
Bear in mind this includes docs, tests, support for multiple dev boards, simulation, and compiled software in Verilog $readmemh format.
Flux