Graham Sutherland / Polynomial
for some reason I can't 100% convince myself that I'm right here, so just to double check: if I have a pair of 100kHz source clocks with some constant phase relationship, and I use a pair of discrete PLL ICs to generate 10MHz clocks from those, the resultant clocks will still share the same phase relationship, yes? (minus some small error introduced by the process)
Jan 31 at 6:25pmWeb
Show threadDarrell HarmonJan 31

@gsuberland They will have the same time offset as the original pair of 100 kHz clocks. The phase offset will be multiplied by the same factor of 100 as the frequency.

One of the output edges will align to an input edge.

Assumes a simple PLL with only an N divider.

Show threadGraham Sutherland / PolynomialJan 31
@dlharmon ahhh, ok. that makes things more wonky.
Show threadpenguin42Jan 31
@gsuberland I don't see why they would be guaranteed to have the same relationship; you could slip by a 100kHz cycle as one of the PLLs was starting up.
Show threadGraham Sutherland / PolynomialJan 31
@penguin42 wouldn't that still leave them in the same phase, since you'd be slipping by 2π?
Show threadGraham Sutherland / PolynomialJan 31
@penguin42 (although Darrell's answer suggests that it'd be shifted by time, not phase, which complicates things)
Show threadRF_TomJan 31
@gsuberland when the PLLs are integer n and the loop filter is not totally off - yes. but depending on the actual PLL used there can be an offset due to the reference signal symmetry / duty cycle. if you have the option use FF fref doubling and then div/2 to force 50% dty cycle. if you must use fractional n use one with a sync strobe input to reset the counters and sigmadelta accumulators simultaneously after initial lock is achieved
Show threadRF_TomJan 31
@gsuberland also if there is an option to activate charge pump bleed current it generally improves the phase coherence between different outputs generated from the same source, as the phase frequency discriminator is in its lowest gain region when lock is achieved. this is especially true when using VCXOs. CP bleed current allows the PFD to have more control authority even there is a small phase offset. +/- bleed depends on the loop filter/vco voltage response
Show threadRF_TomJan 31
@gsuberland and/or small loop filter BWs
Show threadGraham Sutherland / PolynomialJan 31
@RF_Tom TIL, thanks for the info!
Show threadPhilip BraggJan 31
@gsuberland the relationship depends on the type of phase detector you use.