for some reason I can't 100% convince myself that I'm right here, so just to double check: if I have a pair of 100kHz source clocks with some constant phase relationship, and I use a pair of discrete PLL ICs to generate 10MHz clocks from those, the resultant clocks will still share the same phase relationship, yes? (minus some small error introduced by the process)
@gsuberland They will have the same time offset as the original pair of 100 kHz clocks. The phase offset will be multiplied by the same factor of 100 as the frequency.
One of the output edges will align to an input edge.
Assumes a simple PLL with only an N divider.