for some reason I can't 100% convince myself that I'm right here, so just to double check: if I have a pair of 100kHz source clocks with some constant phase relationship, and I use a pair of discrete PLL ICs to generate 10MHz clocks from those, the resultant clocks will still share the same phase relationship, yes? (minus some small error introduced by the process)
@gsuberland I don't see why they would be guaranteed to have the same relationship; you could slip by a 100kHz cycle as one of the PLLs was starting up.
@penguin42 wouldn't that still leave them in the same phase, since you'd be slipping by 2π?
@penguin42 (although Darrell's answer suggests that it'd be shifted by time, not phase, which complicates things)