Graham Sutherland / Polynomialfor some reason I can't 100% convince myself that I'm right here, so just to double check: if I have a pair of 100kHz source clocks with some constant phase relationship, and I use a pair of discrete PLL ICs to generate 10MHz clocks from those, the resultant clocks will still share the same phase relationship, yes? (minus some small error introduced by the process)
RF_Tom@gsuberland when the PLLs are integer n and the loop filter is not totally off - yes. but depending on the actual PLL used there can be an offset due to the reference signal symmetry / duty cycle. if you have the option use FF fref doubling and then div/2 to force 50% dty cycle. if you must use fractional n use one with a sync strobe input to reset the counters and sigmadelta accumulators simultaneously after initial lock is achieved
@gsuberland also if there is an option to activate charge pump bleed current it generally improves the phase coherence between different outputs generated from the same source, as the phase frequency discriminator is in its lowest gain region when lock is achieved. this is especially true when using VCXOs. CP bleed current allows the PFD to have more control authority even there is a small phase offset. +/- bleed depends on the loop filter/vco voltage response
@gsuberland and/or small loop filter BWs
@RF_Tom TIL, thanks for the info!