It's #FPGAFriday already! This week, I've got some 1280x720 ULX3S graphics designs for you. Please give them a try and let me know how you get on. This is my first attempt at graphics on ECP5. #FPGA #RadionaOrg
Find the Verilog source & Makefile in git: https://github.com/projf/projf-explore/tree/main/graphics/fpga-graphics
I've created two clock modules for the ULX3S. 25.2 MHz for 640x480 60Hz and 74 MHz for 1280x720 59.8 Hz.
I didn't manage to create a 74.25 MHz clock for 1280x720 60 Hz, but 74 MHz is still in spec 74.25±0.5%.
Clock modules source: https://github.com/projf/projf-explore/tree/main/lib/clock/ecp5
@WillFlux Works fine for me! 🎉️
Maybe you could mention to install the udev rules from here: https://github.com/emard/ulx3s-bin
And the `--write-flash` option for OpenFPGALoader. I always have to carry the FPGA board to the monitor ;)
@mole99 thank you for testing! 🙏
And for the excellent suggestions. I will add write-flash to the README. I’m planning to mention the udev rules in a forthcoming post on OSS CAD Suite.
Flux
mole99