It is legitimately bugging me that I seem to be the only person who wants to be able to buy an ARM or RISC-V or MIPS or SPARC CPU, implemented with an inexpensive FPGA, with a standard parallel memory bus.
I feel stupid for wanting to be able to take such a thing, stick two or four 8/16 bit wide SRAMS and ROMs on it, and have a play like it was Real Hardware™.
@mos_8502 The only real limitation here is that it's hard to get inexpensive FPGAs in a package with so many physical pins, especially a more hobbyist friendly package (not a dense BGA, etc). Given that constraint, most pre-existing designs are tuned for lower pin count buses and more integration (there's plenty of space in the fabric for peripherals too).
PicoRV32 will fit in 1-2K CLBs and supports a very simple 32bit memory interface and a simple custom IRQ interface.
https://github.com/YosysHQ/picorv32
@mos_8502 Of the approachable Lattice ICE40 parts, if you want 44+ IOs (to allow 24A + 16D + control/cs/irq lines), and a non-BGA package, that's an ICE40HX with ~3K CLBs in a 20x20 LQFP144 package. ~$10 for singles at Mouser or Digikey. Not a lot of elbow room, but a minimal RV32I would be doable. There are a couple smaller parts but they only have ~1K LEs which is going to be very tight.
The more powerful ECP5 family has some 98IO 3/6/11K CLB 144LQFP options for ~$15/20/40 in singles.
@mos_8502 I guess I was just misunderstanding your complaint as a "I wish this was doable" (to which I feel like the answer is "it is, but not in a terribly optimal way") rather than "I wish somebody had built it and was offering one for sale".
I suspect it's a niche product -- wanting a more modern RISC-y CPU but with no integrated peripherals, a traditional parallel bus (but wider enough that many would find it awkward to work with), and packaged as a DIP64 footprint and/or castellated PCB.
@mos_8502 Agreed, and trying to interface to it with some ports or what nots isn’t fun at all, nor effective.
That said, I’m generally more into accelerators for existing systems (cheap!) than whole new systems. A dirt cheap IIGS accelerator would be good.
@mos_8502 RISC-V is probably your best chance for FPGA implementation (there are a bunch of open source cores). But all the architectures you mention are 32 bit (or 64 bit), so external pin count is rapidly a limitation on “inexpensive” :-/
Maybe the original 8088 approach of multiplexing the data bus and address bus could bridge the gap? It’s (much!) slower, and needs external address/data latching. But could fit in 16 data/address pins + control pins 🤔
@ewenmcneill Let's say it's a hypothetical RISC-V variant, which is 32-bit internally, but has a 16-bit data bus (like the old 68K CPUs) and a 24-bit external address bus (32 internally, top bits always 0). That's 40 pins right there. You'd also need:
/IRQ
/NMI
/RES
CLK (input or output, whichever is more convenient)
R/W or a /RD and /WR pair
So let's call it 46 I/O pins needed, and a RISC core that knew how to handle spreading a 32-bit read or write over 2 cycles.
@ewenmcneill If it's on a small PCB with components only on the top side, it can have Pi Pico style castellated holes for board mounting. Make it a square-ish board, with a notch on a corner to signify pin 1. Say you need a power and ground on each side, so that's 13 castellated holes per side, 2.54mm pitch, that's ~30mm per side, call it 35mm square just to be safe.
Use a BGA package FPGA, give it the regulator and capacitor support bits it needs on the module, so it can talk 3.3V bus.
@mos_8502 using a BGA-style FPGA and a four sided (square) castellated “module” is a good idea.
But even ~46 I/Os is taking you to the top end of the iCE40 range, or the lower end of the ECP5 range (and it might need ECP5 for logic). Looks like an ECP5 12K LUT with 90-200 I/Os is US$12-20 (depending on package/quantity). So the full module, with support chips, etc, is probably still ~US$100. Which I guess is still plausible.
@mos_8502 8K 4-LUTs is fairly small for a RISC-V 32 bit CPU, but people have definitely put microcontroller class RISC-V CPUs into them, which is possibly what you want anyway.
The ECP5 LFE5U-12F-6BG256C is also about US$12-15, and has 1.5x more LUTs and more I/O pins. Which would leave more room for eg memory bus logic.
Both are 1.4-1.5V core though, so non-trivial power management.
(Link is NZ$)
@mos_8502 yes, it’s pretty common for FPGAs to support 3.3V I/O, but have a lower (ie faster, cooler) internal logic. They’ve got voltage converters at the edge I/Os (you just give them 2+ supply voltages, in the right order — VCC core and VCC IO).
IIRC both iCE40 and ECP5 are like that.
@mos_8502 people have run FPGA based CPU cores from even SPI flash directly (execute in place), without extra clocks. I think they just stall the memory bus for extended periods, so it’s quite slow.
But yes starting with “long memory fetched cycles” from ROM and then copying into “faster fetch cycles” RAM is pretty common.
@funkylab Let's say it's a hypothetical RISC-V variant, which is 32-bit internally, but has a 16-bit data bus (like the old 68K CPUs) and a 24-bit external address bus (32 internally, top bits always 0). That's 40 pins right there. You'd also need:
/IRQ
/NMI
/RES
CLK (input or output, whichever is more convenient)
R/W or a /RD and /WR pair
So let's call it 46 I/O pins needed, and a RISC core that knew how to handle spreading a 32-bit read or write over 2 cycles.
@funkylab If it's on a small PCB with components only on the top side, it can have Pi Pico style castellated holes for board mounting. Make it a square-ish board, with a notch on a corner to signify pin 1. Say you need a power and ground on each side, so that's 13 castellated holes per side, 2.54mm pitch, that's ~30mm per side, call it 35mm square just to be safe.
Use a BGA package FPGA, give it the regulator and capacitor support bits it needs on the module, so it can talk 3.3V bus.
@mos_8502 yeah, the problem really will be spec'ing this for low price; can't do it with less than ca 48 GPIOs , and there's simply cost to having enough silicon die to connect that many pads/balls/pins, so the cheapest FPGA families probably won't do. and then we're pretty quickly in >11€/piece territory for the FPGA… add in 1€ for config memory, 1€ for power, 1€ for passives, plus PCB, plus assembly.
Honestly, I could see me spinning a cheap 4-layer board for such an endeavor, but even if …
@mos_8502 upfront R&D, prototype costs,
then your price would have to be (taxes+per piece fees)+(R&D cost)/1000 above per-piece costs.
costs: 11€ per FPGA, (cheapest I can find on LSCS,), 4€ other components, 5€ board and assembly costs = 19 € per piece
Say you need another 45s per piece for programming, a minimal functional test, and putting a sticker saying "MIPS" on it, and you do that for 30 €/hr (smwhat minimum cost for labor from POV of an employer), incl sticker you're down +50ct;
Cmod A7 The Cmod A7-15T variant is now retired and no longer for sale in our store. The Cmod A7-35T is still available. The Digilent Cmod A7 is a small, 48-pin DIP form factor board built around a Xilinx Artix 7 FPGA. The board also includes a USB-JTAG programming circuit, USB-UART bridge, clock source, Pmod host connector, SRAM, Quad SPI Flash, and basic I/O devices. These components make it a formidable, albeit compact, platform for digital logic circuits and Microblaze embedded softcore p…
@guidoism I think for the scale we’re talking, unless we got sponsored, FPGA would be the way to go. I’d love an inexpensive, simple to use, CPU-Only RISV-V or MIPS or SPARC open hardware ASIC, but that’s a lot more money than I think could be raised.
So treat the FPGA as a poor man’s ASIC. Put the programming pins of the config flash on the external pins, make it as minimal as possible, expose a plain static memory bus.
@mos_8502 I know. I know. I’m not ready to give up on this dream though. I know if it happens it’s going to be many many years away and will depend on the shuttles getting even cheaper (I don’t know if they are already at the floor) maybe @matthewvenn can comment.
In the meantime I’m going to get a part onto a Tiny Tapeout run in order to get comfortable with the process. I’m going to concentrate on getting a WISC-style “macro”-processor on $2 10x10 cm PCB that can be used for experimentation.
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