It is legitimately bugging me that I seem to be the only person who wants to be able to buy an ARM or RISC-V or MIPS or SPARC CPU, implemented with an inexpensive FPGA, with a standard parallel memory bus.
I feel stupid for wanting to be able to take such a thing, stick two or four 8/16 bit wide SRAMS and ROMs on it, and have a play like it was Real Hardware™.
@mos_8502 RISC-V is probably your best chance for FPGA implementation (there are a bunch of open source cores). But all the architectures you mention are 32 bit (or 64 bit), so external pin count is rapidly a limitation on “inexpensive” :-/
Maybe the original 8088 approach of multiplexing the data bus and address bus could bridge the gap? It’s (much!) slower, and needs external address/data latching. But could fit in 16 data/address pins + control pins 🤔
@ewenmcneill Let's say it's a hypothetical RISC-V variant, which is 32-bit internally, but has a 16-bit data bus (like the old 68K CPUs) and a 24-bit external address bus (32 internally, top bits always 0). That's 40 pins right there. You'd also need:
/IRQ
/NMI
/RES
CLK (input or output, whichever is more convenient)
R/W or a /RD and /WR pair
So let's call it 46 I/O pins needed, and a RISC core that knew how to handle spreading a 32-bit read or write over 2 cycles.
@ewenmcneill If it's on a small PCB with components only on the top side, it can have Pi Pico style castellated holes for board mounting. Make it a square-ish board, with a notch on a corner to signify pin 1. Say you need a power and ground on each side, so that's 13 castellated holes per side, 2.54mm pitch, that's ~30mm per side, call it 35mm square just to be safe.
Use a BGA package FPGA, give it the regulator and capacitor support bits it needs on the module, so it can talk 3.3V bus.
@mos_8502 using a BGA-style FPGA and a four sided (square) castellated “module” is a good idea.
But even ~46 I/Os is taking you to the top end of the iCE40 range, or the lower end of the ECP5 range (and it might need ECP5 for logic). Looks like an ECP5 12K LUT with 90-200 I/Os is US$12-20 (depending on package/quantity). So the full module, with support chips, etc, is probably still ~US$100. Which I guess is still plausible.
@mos_8502 8K 4-LUTs is fairly small for a RISC-V 32 bit CPU, but people have definitely put microcontroller class RISC-V CPUs into them, which is possibly what you want anyway.
The ECP5 LFE5U-12F-6BG256C is also about US$12-15, and has 1.5x more LUTs and more I/O pins. Which would leave more room for eg memory bus logic.
Both are 1.4-1.5V core though, so non-trivial power management.
(Link is NZ$)
@mos_8502 yes, it’s pretty common for FPGAs to support 3.3V I/O, but have a lower (ie faster, cooler) internal logic. They’ve got voltage converters at the edge I/Os (you just give them 2+ supply voltages, in the right order — VCC core and VCC IO).
IIRC both iCE40 and ECP5 are like that.
@mos_8502 people have run FPGA based CPU cores from even SPI flash directly (execute in place), without extra clocks. I think they just stall the memory bus for extended periods, so it’s quite slow.
But yes starting with “long memory fetched cycles” from ROM and then copying into “faster fetch cycles” RAM is pretty common.
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Ewen McNeill
Guido Bartolucci