A Tiny FABulous FPGA on Tiny Tapeout? It's more likely than you think!

Yesterday the TTIHP26a shuttle (https://app.tinytapeout.com/shuttles/ttihp26a) from #TinyTapeout has closed. In it, hundreds of incredible projects.
You can view the full shuttle and its designs here: https://app.tinytapeout.com/projects/3744

I had the opportunity to submit an FPGA, which I created using my FABulous LibreLane plugin. For this fabric, I developed a "tiny" tile library that better fits the constraints of Tiny Tapeout.

#FPGA #ASIC #TinyTapeout

We now have working #tinytapeout templates for Spade!

For IHP: https://github.com/spade-lang/ttihp-spade-template
For Sky130: https://github.com/spade-lang/ttsky-spade-template

The IHP shuttle closing in 5 days is full, But! if you are a Swiss resident you can still get on there and get the chip manufactured for free 🇨🇭

This also came with the nice benefit of me finally making swim download the compiler binaries instead of rebuilding for every project, so initial builds of other Spade projects are much faster

🛰️ A #RISC-V CPU developed by students at JMU Würzburg was integrated into the HUNITY satellite by #BME university and successfully activated in space. 🌍✨

At 527 km altitude and 7.6 km/s, the chip executed its first test program flawlessly — proving reliable operation under real orbital conditions.

Thanks to @tinytapeout for this opportunity

#TinyTapeout #RISCv #SpaceTech #NewSpace

https://www.informatik.uni-wuerzburg.de/ce/news/single/news/risc-v-prozessor-der-universitaet-wuerzburg-erfolgreich-im-weltall/

Thank you @tnt for bringing up my TinyQV RISC-V SoC on the most recent #TinyTapeout chips to come back from the fab.

These particular IHP chips are funded by the EU, so sadly due to Brexit they can't be shipped to me - but we were able to get Micropython running, and therefore confirm the design is working pretty well.

Primarily due to better IO pads on the IHP chips, this version runs significantly faster than the previous sky130 tapeout - tnt had it running at 100MHz on one version. The other didn't quite make that, but ran OK at 98MHz - that's quite a bit faster than the 64MHz design frequency!

1/5 My two demos, Warp and WhyNot? won 1st place in 'Graphics' (Warp) and 1st place in 'Best for size' and 'Single tile' (WhyNot?) at the #TinyTapeout tt08 demo competition. Huge thanks to the jury for the recognition. This means a lot to me, I started hardware design from scratch in 2018, and this turned into a big adventure.

https://m.youtube.com/watch?v=il_qKTiyKLY

Stoked to interview @mithro about https://wafer.space this Tuesday – kicking off a new season of #HacksterCafe ! Learning a bunch about custom, low-cost, #OpenSource #silicon fab... Excited for the updates on last Nov's @crowdsupply campaign, and to see what questions people drop in the chat 👀

We're scheduled later than usual due to time zones. Hope to see you there!
3:30pm Pacific / 6:30pm Eastern / 11:30pm UTC
➡️ https://www.youtube.com/watch?v=HpBEOXHUzHE
➡️ https://www.linkedin.com/events/7426800975115493376

#TinyTapeout #HacksterIO

How can you fit a retro tunnel effect with a sound track in 161x225 μm of silicon? Checkout my detailed write up on making a demo entry to the #TinyTapeout tt08 competition: https://github.com/sylefeb/tt08-compo-entry/blob/main/docs/info.md

https://www.youtube.com/watch?v=ELOYGwZgHnw

1/3) Wow, TT08 #TinyTapeout including all demoscene entries landed and I had no clue, imagine my surprise discovering all the fantastic demos (see below, thx bitluni!) on actual hardware. Kudos to all contributors and the team!!

https://www.youtube.com/watch?v=A9BhSaqL7jg