Last week I got some chips backs containing a SKY130 Register File macro I designed from scratch. Basically a 2R1W SRAM macro 32x32.

And so far all the testing I did has been good 🎉

This is far from fully tested, _lots_ to do but still it's very cool to see.

That #tinytapeout chip included several designs using it. One designed for caracterization , but also several "show cases" ones.

Just listening to The Amp Hour featuring Julia Desmazes.

https://theamphour.com/721-chip-design-for-fun-and-waffles-with-julia-desmazes/

Lots on #hardware / #FPGA / chip design, #tinytapeout, and how to get started.

https://essenceia.github.io/ 👈🧐

So much good stuff to discover!

She uses @archlinux btw. ^^

Just for fun I've been sort of abusing the differential receiver ( clk + data + deserializer ) project that I had in TT08. It occured to me it should work fine for MIPI-CSI. So I wired a RPi v1 camera to it, and capture the deserialized output with a logic analyzer and I can extract image data out of it 🎉

The RPi camera is 2 lanes and I can only capture one, so I'm missing half the data and there are a lot of hacks to compensate for that but ... it's possible to RX MIPI in #tinytapeout !

We already have some nice looking entries into our #demoscene competition!

There's still 33 days to go, but don't leave it too late! Start on your entry today:

https://tinytapeout.com/competitions/demoscene-ttsky26a-announce/

#ASIC #opensource #TinyTapeout

A Tiny FABulous FPGA on Tiny Tapeout? It's more likely than you think!

Yesterday the TTIHP26a shuttle (https://app.tinytapeout.com/shuttles/ttihp26a) from #TinyTapeout has closed. In it, hundreds of incredible projects.
You can view the full shuttle and its designs here: https://app.tinytapeout.com/projects/3744

I had the opportunity to submit an FPGA, which I created using my FABulous LibreLane plugin. For this fabric, I developed a "tiny" tile library that better fits the constraints of Tiny Tapeout.

#FPGA #ASIC #TinyTapeout

We now have working #tinytapeout templates for Spade!

For IHP: https://github.com/spade-lang/ttihp-spade-template
For Sky130: https://github.com/spade-lang/ttsky-spade-template

The IHP shuttle closing in 5 days is full, But! if you are a Swiss resident you can still get on there and get the chip manufactured for free 🇨🇭

This also came with the nice benefit of me finally making swim download the compiler binaries instead of rebuilding for every project, so initial builds of other Spade projects are much faster

🛰️ A #RISC-V CPU developed by students at JMU Würzburg was integrated into the HUNITY satellite by #BME university and successfully activated in space. 🌍✨

At 527 km altitude and 7.6 km/s, the chip executed its first test program flawlessly — proving reliable operation under real orbital conditions.

Thanks to @tinytapeout for this opportunity

#TinyTapeout #RISCv #SpaceTech #NewSpace

https://www.informatik.uni-wuerzburg.de/ce/news/single/news/risc-v-prozessor-der-universitaet-wuerzburg-erfolgreich-im-weltall/

Thank you @tnt for bringing up my TinyQV RISC-V SoC on the most recent #TinyTapeout chips to come back from the fab.

These particular IHP chips are funded by the EU, so sadly due to Brexit they can't be shipped to me - but we were able to get Micropython running, and therefore confirm the design is working pretty well.

Primarily due to better IO pads on the IHP chips, this version runs significantly faster than the previous sky130 tapeout - tnt had it running at 100MHz on one version. The other didn't quite make that, but ran OK at 98MHz - that's quite a bit faster than the 64MHz design frequency!

1/5 My two demos, Warp and WhyNot? won 1st place in 'Graphics' (Warp) and 1st place in 'Best for size' and 'Single tile' (WhyNot?) at the #TinyTapeout tt08 demo competition. Huge thanks to the jury for the recognition. This means a lot to me, I started hardware design from scratch in 2018, and this turned into a big adventure.

https://m.youtube.com/watch?v=il_qKTiyKLY