IT WORKS!!!

With a bit of effort I can now receive data from the UART on my keyboard controller, into the CPLD and read it form BASIC on my 6502 laptop revision b (slim version).

I've set the Keyboard controller to output characters from $20 to $7F, here you can see them being shown.

There is also a "new data received" status register too!

#CPLD #LT6502B

Well the CPLD UART is coming along, another big step... Now when it's done receiving a byte, it transfers it to a register, which can then be read at anytime by the CPU. So that the CPU doesn't read garbage if it tries to read mid transfer (double buffer).

more to do yet as I need two such registers and I also want the register to be cleared once it's been read, but this is BIG progress.

This is all done in WINCUPL, not VHDL/Verilog.

#CPLD #LT6502b

Ok, so, I have the next part working of my CPLD UART... it now populates a buffer, with the correct values!!
Green = serial in (LSB first),
Orange is parallel out (LSB at the bottom)

Next step is to transfer that to a register that can be read!

I will probably up my sample clock to 16x, as that seems like the common thing, and 4x may not be 100% reliable. But for simulation, 4x is enough.

#CPLD #LT6502b

Fun with WinSim.

After much battling with dodgy tools from the 90s, I've now got two useful signals. One to start the UART receive and it's counter, and one to stop when the 10th bit is received.

Tomorrow, shift register to capture the bits.

#Retrocomputing #LT6502b #CPLD