Mastodawn

@kubikpixel Ascon-Hash256, just because it just passed finals and can be implemented compactly (and AIU efficiently accelerated with #RISCV bitmanip), sharing code with the Ascon-AEAD128 standardized with it.
Also, it's kind'a regional crypto for me :-)
https://nvlpubs.nist.gov/nistpubs/SpecialPublications/NIST.SP.800-232.pdfhttps://nvlpubs.nist.gov/nistpubs/SpecialPublications/NIST.SP.800-232.pdf

commander 3d ago

NVIDIA on RVA23: “We Wouldn’t Have Considered Porting CUDA to RISC-V Without It” – RISC-V International

https://lemmy.world/post/34793534

NVIDIA on RVA23: “We Wouldn’t Have Considered Porting CUDA to RISC-V Without It” – RISC-V International - Lemmy.World

Lemmy

Natanael Copa 4d ago

For days I have been trying to get a working config for spacemit k1. OrangePi RV2 boots now, but Bananapi BPI-F3 does not, and I have no idea why.

#RISCV #AlpineLinux

knoppix 6d ago

🆕 Debian 13 "Trixie" is officially released 🐧
Built on Linux Kernel 6.12 (LTS) with real-time support ⚙️

Now includes full RISC-V 64 support 📦
APT 3.0 debuts with improved package resolution & color output 🎨
Installer adds HTTP Boot, Btrfs rescue, and better ARM/Mac support 💻
/`tmp` now uses RAM by default 🧠
Updated GNOME 48, KDE Plasma 6.3, Xfce 4.20 & more 🖥️

@itsfoss

https://news.itsfoss.com/debian-13-release/

#Linux #FOSS #Debian #OpenSource #Privacy #Security #SysAdmin #RISCV #FOSS #DevOps #Gnome #OS @tech

Debian 13 "Trixie" Released: What’s New in the Latest Version?

A packed release you can't miss!

It's FOSS News

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AS 396507 6d ago

Our lead relay engineer @alexhaydock has increased our stateless #Tor exit relay deployment to 96! (+1 because of the new #RISCV bare-metal node, +1 other we redeployed due to a silly spelling error). We're stress testing our three AMD Epyc 7402P servers that use #Proxmox.

Each one of the 96 Tor exit nodes are diskless Unified Kernel Images, 56MB in total size, using @alpinelinux's alpine-make-rootfs with an absolutely bare minimum number of packages. We'll be publishing more about our new architecture and configuration soon.

#AlpineLinux #privacy #anonymity #AntiCensorship #AccessToInformation #TorOps #TorOperators

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Andy Newton Aug 16

@rwa @woody Now you have my curiosity up. What are the requirements that require you to target #riscv if you don’t mind me asking? And how usable is the DC board for the Framework? From what I can tell, there are still no desktop-class processors on the market, though things are close.

🇺🇦 haxadecimal Aug 16

My friend @Needlesscomplexity has posted two articles about RISC-V assembly language techniques to his substack:
https://needlesscomplexity.substack.com/p/efficient-risc-v-range-checking
https://needlesscomplexity.substack.com/p/efficient-sign-extension-on-risc
And a library of useful integer operations:
https://needlesscomplexity.substack.com/p/rvint-integer-mathematical-library
I did a lot of assembly language programming back when dinosaurs still roamed the earth, and there are still some valid use cases even today. I firmly believe that having a grasp of assembly language also helps one write better HLL code.
#riscv #assembly

Efficient RISC-V range checking

Using the addi/sltiu instructions effectively

Benard’s Substack

Stewart X Addison Aug 15

Grrr. binutils 2.43 doesn't build #riscv when using Ubuntu 22.04 (or 20.04) as the "linux-libc-dev" package doesn't have the "asm/hwprobe.h" header file. binutils-2.42 didn't need it. 2.45 has a check for it and will tolerate its absence. I guess I'll use 2.45 for my openjdk devkit for jdk25u...