TSMC N3B fabbed Compute Tile hosts four #LionCove-based Performance (P) cores, sharing 12MB of L3 cache, with 2.5MB of private L2 cache per P-core. As opposed to #ArrowLake, the Skymont-based efficiency core cluster (E) doesn't share the same L3 cache pool, but sits on a "Low Power Island" with its own dedicated L2 cache (4MB). Next to E-cores is the NPU for almost 48 TOPS of #AI performance.
https://www.tomshardware.com/pc-components/cpus/intels-lunar-lake-intricacies-revealed-in-new-high-resolution-die-shots
