Further investigations with #Psion ramdrive shenanigans, this time including the 3mx in MAME (which currently has 512KB). Plus some other notes on the hardware, some guesses, MAME debug tools, and a small but helpful #EDisAsm update.
512K
In this mythical device (emulated in MAME), the root of M: starts at page 07, 0xDFF0. Ramdrive filesystem blocks are 256 bytes on this machine, so smaller than normal for FAT12 (they're 512 bytes on the 2MB 3mx).
The astute among you will have noticed that page 07 is the last block in 512K RAM. From 0xDFF0, blocks for M: are added in reverse order. So the block for the first file is at 0xDEF0, then 0xDDF0, then 0xDCF0, etc etc.
This is what I'd assumed would happen with all models of the 3mx - root record at the top of RAM, then working backwards so that normal working RAM doesn't interfere with the ramdrive. But that isn't the case with the 2MB model (starting in page 08, working up from 0x4200, and probably isn't with 4MB (currently looking like page 08, working up from 0x6660, but still broken). I haven't checked with older ASIC9 devices yet (3a, 3c, Siena, Workabout 1).
Also, I got it wrong before: 512K model is 1x 4Mbit chip (256Kbit * 16 bits), not 2 chips.
ASIC9MX
According to the SDK, ASIC9 can address up to 16MB RAM. It has 4 RSEL lines (used in the ASIC9MX as chip selects), and 2 CSEL lines (upper and lower halves of the 16 bits). AFAIK, each window is 2MB (pages 0x00 to 0x1F). So how on earth does it fit in 16MB when it only has the space for 8MB? Unless it does something from 0x80 onwards? (EDIT: It does! My current guess is that it uses column 9 to switch between 00-7F and 80-FF).
Current Assumptions for 3mx
This is pages 00-7F. This is all mirrored at pages 80-FF.
- 512KB: pages 00, 08, 10 and 18 are mirrors. Then the same for {01, 09, 10, 19}, {02, 0A, 12, 1A} ... {07, 0F, 17, 1F}. Nothing but static after that.
- 1MB: same as above, then repeated for {20, 28, 30, 38}, {21, 39, 31, 39} ... {27, 2F, 37, 3F}. Nothing after that.
- 2MB: only 00-1F and that's it. No mirrors, everything above is static from floating pins. (We know this for sure.)
- 4MB: 00-3F, no mirrors, everything above is static.
I could really do with some more 3mx (or Workabout mx, which is basically the same machine in a different form factor) boards and appropriately sized RAM chips to see what they do.
EPOC16
I'm currently testing with EPOC16 4.08F. However, I have a French machine with 4.14F and a Workabout mx with 4.31F. Both of these could have bug fixes that sort the issues with more than 2MB RAM.
For all I know, it might have the same issue with 1MB (2x512K), and it's some bug with running two chips on this version of EPOC16.
If anyone has a 3mx or Workabout mx with a newer version of EPOC16 (I can tell you how to work it out) then please let me know. We could use your ROM for testing.
EDisAsm
Some slight mods, but they make a difference. Rather than use one universal bank/page number, it now uses four separate variables for the four separate banks
psel0 for RAM Bank 1 (addr 0x6:0000)psel1 for RAM Bank 2 (addr 0x7:0000)psel2 for ROM Bank 1 (addr 0x8:0000)psel3 for ROM Bank 2 (addr 0x9:0000)
(N.B.: psel is Psion speak for "page select")
You can now set these individually from the command line in EDisAsm. So I can have psel0 at RAM page 08, psel1 at RAM page 19, psel2 at ROM page 9A, and psel3 at ROM page 80.
Now when using db and dw to dump bytes or words to the screen, it will auto-detect which block of memory you're in and will use the correct psel accordingly.
The implementation needs a lot of tidying under the hood, but it works much better than before.
MAME
I've worked out how to dump the RAM in MAME without having to use EDisAsm. This is handy, because serial isn't implemented yet in the 3c or 3mx machines in MAME. You need to use the MAME's debug command prompt:
save asic9ram.dmp,0:asic9:asic9_ram,1000000
Other tests are currently happening in MAME with different RAM sizes, but that's not my work. Stay tuned!