Mastodawn

alios Mar 9, 2025

Oh falls ihr wegen der Arbyte oder wegen Toy Projekt weg von Asien und US Silizium kommen wollt, schaut Euch mal den #cva6 an: Ist ne 6-stage pipeline #riscv (32/64bit) Implementierung die #fpga und #asic ready und gut verifiziert ist. Basiert auf der Arbeit der ETH Zürich, wurde dann von Thales aus Frankreich weiter entwickelt und wird nun durch die OpenHW Group betreut - also nen echtes Europa Dings:

https://github.com/openhwgroup/cva6

#hardware #embedded

GitHub - openhwgroup/cva6: The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux. - openhwgroup/cva6

GitHub

Giuseppe Michieli May 23, 2024

#Virus associated with severe #HFMD found evolving with #risks of #outbreak: #China #CDC, https://www.globaltimes.cn/page/202405/1312928.shtml

#Coxsackievirus A6 (#CVA6), associated with severe hand, foot, and mouth disease (HFMD), is evolving and presents a risk of outbreak occurrence, according to research from the Chinese Center for Disease Control and Prevention (Chinese CDC). An immunologist told the Global Times on Thursday that vaccines would be an effective form of prevention.

Virus associated with severe HFMD found evolving with risks of outbreak: Chinese CDC - Global Times

Jarkko Sakkinen Jan 11, 2024

cool my #riscv #keystone page table bootstrapping fixes for #cva6 are all merged to upstream. i debugged the issues over a month so nice to see that it was worth it. actually learning how #opensbi is implemented was in all cases definitely a good lesson to learn.

Akkoma

Jarkko Sakkinen Dec 3, 2023

Does Rust #Linux already have bindings for network drivers? I’m thinking of making #lowRISC Ethernet driver because the one provided by OpenHW Group is a corpse. It is like made for v5.7 and since not updated. This is the one that is used in #CVA6.

#rustlang

Akkoma

RISC-V Nov 28, 2023

RT from OpenHW Group (@openhwgroup)

Great to get #OpenHW and our #RISCV #CVA6 Platform, which is for vendor neutral SW testing, mentioned by @ndahad of @embedded_online

Need an industrial grade, fully verified Open Source RISC-V CPU? Try our CORE-V now! #corev
https://www.embedded.com/new-risc-v-processors-address-demand-for-open-source-and-performance/

Original tweet: https://twitter.com/openhwgroup/status/1729473085315891462

RISC-V processors meet demand for open source & performance

RISC-V Summit sees new processors from Synopsys and Ventana, shows traction among firms like Qualcomm, and new OpenHW Group platform.

Embedded.com

Benjamin Carr, Ph.D. 👨🏻‍💻🧬Nov 12, 2023

Boffins from ETH Zurich have devised a novel #fuzzer for finding bugs in #RISCV chips and have used it to find more than three dozen.
When applied to six actual RISC-V #CPU – #VexRiscv, #PicoRV32, #Kronos, #CVA6, Rocket, and BOOM – Cascade found 37 new bugs (translating to 29 #CVE) in five of these six designs. https://www.theregister.com/2023/10/24/cascade_fuzzer_zurich/

Hot fuzz: Cascade finds dozens of RISC-V chip bugs using random data storm

ETH Zurich boffins say they've devised a better CPU fuzzer to find flaws

The Register

RISC-V Nov 8, 2023

RT from Flo (@FlorianWoh)

Nice Stephen of @RedHat giving some background and also mention the project Red hat run with the @openhwgroup for a vendor neutral RISC-V Software testing platform

#riscv #redhat @jefro_net #fedora #CVA6 #CVA6platform #openHW

Link to Platform info:
https://www.openhwgroup.org/news/2023/11/07/openhw-group-announces-core-v-cva6-platform-project-for-risc-v-software-development-and-testing/

Original tweet: https://twitter.com/FlorianWoh/status/1722311434221371558

OpenHW Group Announces CORE-v CVA6 Platform Project for RISC-v Software Development & Testing | OpenHW Group

Today, at the RISC-V Summit, the OpenHW Group announced the multi-member CORE-V CVA6 Platform project. The platform is an open-source FPGA-based software …

Jarkko Sakkinen Nov 3, 2023

#CVA6 #PDF #manual: https://readthedocs.com/projects/openhw-group-cva6-user-manual/downloads/ #note

Akkoma

Jarkko Sakkinen Nov 1, 2023

OK, something probably pretty basic with #QEMU I need to ask.

I have this command-line, which is generated by #Keystone #RISCV #TEE build:

/home/jarkkojs/work/keystone/qemu/build/riscv64-softmmu/qemu-system-riscv64 \
   $DEBUG \
   -m 2G \
   -nographic \
   -machine virt,rom=/home/jarkkojs/work/keystone/build/bootrom.build/bootrom.bin \
   -bios /home/jarkkojs/work/keystone/build/sm.build/platform/generic/firmware/fw_payload.bin \
    \
   -netdev user,id=net0,net=192.168.100.1/24,dhcpstart=192.168.100.128,hostfwd=tcp::${HOST_PORT}-:22 \
   -device virtio-net-device,netdev=net0 \
   -device virtio-rng-pci \
   -smp $SMP

QEMU has support for #Spike, which is #CVA6 emulation.

So when I do to the above command-line simply s/virt,/spike,/g, I get this error:

$ build/scripts/run-qemu.sh
**** Running QEMU SSH on port 3617 ****
qemu-system-riscv64: Property 'spike-machine.rom' not found

How do I end up to this error message? Why does it seek a filename like that? Without rom= I can run Spike emulation but I need that bootrom for the application.

Akkoma

Jarkko Sakkinen Oct 24, 2023

I'm trying to get #Keystone #SM ongoing with #CVA6 but stuck with SM's trap handler giving me illegal instruction. I wonder how interpret these values for #mideleg and #medeleg: https://github.com/keystone-enclave/keystone/issues/374#issuecomment-1777032123 #riscv #opensbi