Jan Gray

@jangray
692 Followers
579 Following
432 Posts
computing with FPGAs; former Microsoft dev tools architect; co-chair RISC-V Soft CPU SIG; driving RISC-V composable extensions standardization so we can all build on each other's good work; #FPGA #RISCV manycore accelerator overlays 🇨🇦 🇺🇸
FPGA CPU Newshttps://fpga.org
Ancient FPGA CPU Newshttp://fpgacpu.org
GRVI Phalanx kilocore RISC-V RV64I FPGA overlayshttps://fpga.org/2019/08/19/2grvi-phalanx-at-hot-chips-31-2019/
Composable Custom Extensions for RISC-Vhttps://github.com/grayresearch/cx
Jan GrayAug 23, 2024
Friends, let us go forward together into a future of hope and possibility (and the rule of law).
Jan GrayJan 7, 2024

~38 years ago, Brad Templeton’s Looking Glass Software (where I worked three semesters as a U.Waterloo CS coop student) gave out 50,000 demo floppies of Alice Pascal in Computer Language magazine.

An IDE with syntax director editor, interpreter, debugger, Alice was doomed by the unfamiliarity of (prefix) program tree editing and esp. by the unassailable greatness and momentum of Borland’s Turbo Pascal.

*Curiously* the Canadian publisher dumped the Alice in Wonderland theme in the ad copy.

Jan GrayNov 27, 2023

Don't want to crash that other thread about register windows alternatives but does anyone remember the Sproull Counterflow Pipeline Processor? Was it ever implemented in hardware?

Fun to regard a register file as just a summary of past temporary writes.

https://dl.acm.org/doi/10.5555/974934
https://dl.acm.org/doi/pdf/10.5555/974934

Counterflow Pipeline Processor Architecture | Guide books

Guide books
Jan GrayNov 27, 2023

Just spoke with an ECE prof asking about an end-end undergrad curriculum using RISC-V hard and soft processor SoCs. I recalled this WCAE 2000 paper, presented at ISCA 2000 in Vancouver. Altera Nios was announced that week...

Hands on Computer Architecture: Teaching Processor and Integrated System Design with FPGAs
https://dl.acm.org/doi/10.1145/1275240.1275262
https://dl.acm.org/doi/pdf/10.1145/1275240.1275262

Hands-on computer architecture | Proceedings of the 2000 workshop on Computer architecture education

ACM Other conferences
Jan GrayNov 19, 2023
My Onyx RE2 IO4 board has a bad motivator. Thanks SGI for soldering down an unobtanium battery+NVM+clock chip.
Jan GrayNov 11, 2023
Why yes I am once again working around the clock on this hopefully useful standardization effort.
Jan GrayNov 7, 2023
In his RISC-V Summit Keynote this morning, Meta's Prahlad Venkatapuram makes a compelling case for new RISC-V standard specifications for custom extensions, esp. "unify how these extensions are introduced to software". This has very close alignment with the objectives and use cases for the Soft CPU SIG's draft proposed Composable Extensions specification (which we are preparing as a new task group).
https://github.com/grayresearch/cx
https://github.com/riscv-admin/sig-soft-cpu/blob/main/TG/CX/CHARTER.md
GitHub - grayresearch/CX: Proposed RISC-V Composable Custom Extensions Specification

Proposed RISC-V Composable Custom Extensions Specification - GitHub - grayresearch/CX: Proposed RISC-V Composable Custom Extensions Specification

GitHub
Jan GrayNov 4, 2023
It’s still great to vote in Washington State
Show threadJan GrayNov 3, 2023
The past two decades have been an era of siloed, proprietary, fragmented, duplicative soft processor ecosystems. Use MicroBlaze (or Nios) IP and you were locked in to Xilinx (or Altera) devices.
Show threadJan GrayOct 18, 2023

The worst part of reduced prec FP vector dot product on FPGAs are the LUTs wasted in the muxes within the damned barrel shifters required for denormalizing (pre-aligning) FP addends and normalizing FP sums.

Block FP finesses away most of these shifters, except for the final dot product subtotal for the block.

This is a huuuuuge savings in LUTs. And now both Intel and Achronix have hard block floating point DSPs (Intel AI Tensor Blocks (AITBs) and Achronix Speedster 7t MLPs).