Jan Gray

@jangray
692 Followers
579 Following
432 Posts
computing with FPGAs; former Microsoft dev tools architect; co-chair RISC-V Soft CPU SIG; driving RISC-V composable extensions standardization so we can all build on each other's good work; #FPGA #RISCV manycore accelerator overlays 🇨🇦 🇺🇸
FPGA CPU Newshttps://fpga.org
Ancient FPGA CPU Newshttp://fpgacpu.org
GRVI Phalanx kilocore RISC-V RV64I FPGA overlayshttps://fpga.org/2019/08/19/2grvi-phalanx-at-hot-chips-31-2019/
Composable Custom Extensions for RISC-Vhttps://github.com/grayresearch/cx
The fine traffic generator demo in this video seems to confirm my suspicion that, despite Versal's hard NOC, to access the full bandwidth of HBM2e, anywhere in the fabric, you will have to employ a soft NOC like the Hoplite NOC in the GRVI Phalanx family.
https://fpga.org/2019/08/19/2grvi-phalanx-at-hot-chips-31-2019/
2GRVI Phalanx at Hot Chips 31 (2019): The First Kilocore RISC-V RV64I with High Bandwidth Memory

This week at Hot Chips 31 (2019) I am presenting a status update poster on the work-in-progress GRVI Phalanx Accelerator Kit: 2GRVI Phalanx: Towards Kilocore RISC-V FPGA Accelerators with HBM2 DRAM…

FPGA CPU News

#FPGA Nice video overview of the Versal HBM Series devices
https://youtube.com/watch?v=oKyKAiEpOHU

(which we will now have to transition to after the unwelcome, abrupt, and premature end-of-life of the fantastic Virtex UltraScale+ HBM family (https://docs.amd.com/v/u/en-US/XCN23006). "Killed by AI.")

Tackle Memory Bottlenecks with the Versal HBM Series

YouTube

So please join in and share what is interesting, novel, surprising, frustrating, or fun about your work on RISC-V on FPGAs. Demos encouraged; marketing discouraged. Your talks may be live, or prerecorded, lightning talks, or full talks.

Website:
https://sites.google.com/view/srvs-workshop

Free registration:
https://community.riscv.org/e/m94ufu/

Propose a talk (deadline Oct 13):
https://forms.gle/PUpkQkqZDcv6mfgC8

Soft RISC-V Systems Workshop

We'll have some great FPGA vendor keynotes on their RISC-V platforms, but we also want to hear from you!

Whether you use FPGA RISC-V systems in industry, research, education, or as a hobby, whether closed or open source, whether you bulid CPU cores, SoCs, gadgets, software, or an application, whether this is your tenth system or your first, we want to hear your story!

Soft RISC-V Systems Workshop:
https://sites.google.com/view/srvs-workshop

Thu Nov. 7 & Fri Nov. 8, 8am-12pm PDT, the RISC-V Int'l Soft CPU Special Interest Group is presenting a free online (Zoom) workshop and celebration of the vibrant RISC-V soft processor community. Please spread the word and join us as attendee or presenter.

This workshop aims to be a technically focused, inclusive celebration of the world of RISC-V FPGA Soft Processor Systems, and the great diversity of designs, designers, and applications.

Soft RISC-V Systems Workshop

I've been slowly working on a new version of the Xerox Alto emulator I wrote while at LCM, and I've got it in a state where I'm happy to call it "beta" quality: https://github.com/jdersch/Contralto2. This uses a new-ish, cross-platform UI toolkit, and thus it should (in theory) look and behave identically across all platforms (Windows/Mac/*nix). The release contains a number of curated disk packs as well. If you try it, let me know how it works, and if the docs need any tweaking to make things easier.
GitHub - jdersch/Contralto2: Xerox Alto Emulator

Xerox Alto Emulator. Contribute to jdersch/Contralto2 development by creating an account on GitHub.

GitHub

A periodical reminder that Luca Cardelli's home page is cooler than yours

http://lucacardelli.name/

Friends, let us go forward together into a future of hope and possibility (and the rule of law).
Can we please have a convention every two weeks?

My first paper has just been published in the IEEE solid state circuits magazine!

Tiny Tapeout: A Shared Silicon Tapeout Platform Accessible To Everyone

https://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=4563670

If you're not a member, you can read the pre-print here: https://raw.githubusercontent.com/mattvenn/tt-ieee-paper/main/paper_TT.pdf

IEEE Solid-State Circuits Magazine | Current Issue | IEEE Xplore