This probably deserves its own post:

We've just open sourced a tool that Tim Hutt wrote for #debugging #CHERIoT things. The tool consumes a CPU trace from CHERIoT Ibex and exposes a gdbserver protocol interface. You can then use CHERIoT lldb to step forwards and backwards in your trace.

Mitre has just published their top 25 most dangerous software vulnerabilities of 2025

How does #CHERIoT stack up against this list?

5, 7, 8, 11, 14, and 16 are deterministically mitigated with just a recompile.

13 will trap, but is recoverable on a per-compartment basis.

15 is trivial to mitigate with compartmentalisation. Phil Day wrote about this 18 months ago.

6 is mitigated by good capability-based filesystem APIs.

25 is mitigated by our software capability model in the RTOS.

1, 2, 3, 9, 10, 12, 22, and 23 and are not normally applicable on embedded platforms.

That leaves you with a lot more spare brainpower to think about avoiding the remaining seven (4, 17, 18, 19, 20, 21, and 24). The impact of many of these is limited in an environment where there is a programmer model that makes implementing the principles of least privilege and intentional use trivial.

Here is some cool documentation and opensourcing of xzone malloc with type segregation and MTE support.

https://github.com/apple-oss-distributions/libmalloc/blob/af3c5dc3a540eeec030930b35b1349f4de400206/doc/xzone_malloc.md

You can really call anything RISC-V

(This is what Tenstorrent ships)

The write-up of my new graph layout algorithm for SpiderMonkey is finally live.

We built a custom layout algorithm for JS and WASM that follows the structure of the source code. No more spaghetti nightmares from Graphviz, and thousands of times faster.

https://spidermonkey.dev/blog/2025/10/28/iongraph-web.html

Beyond 2nm #GAAFET Transistors, "gate stack" engineering, a core technology for two-dimensional transistors, which are attracting attention as next-generation semiconductor devices.

The biggest obstacle to commercializing 2D transistors is the implementation of high-quality gate stacks. This research presents a standard blueprint to overcome this challenge.

Also, ferroelectric-embedded gate stacks for memory :)

https://www.nature.com/articles/s41928-025-01448-5