@adrian I feel this. I am currently working on our SystemVerilog Frontend for @verijit and I was surprised how differently you think about Verilog when designing hardware vs when writing a simulator. I mean I knew in theory that Verilog is event driven, but the common subset people actually use does conveniently not run into this much.

I feel like I am actually writing half a synthesis toolchain to make our simulator fast. We gained an entire new intermediate representation for this reason.