Tathar makes stuff

@[email protected]
93 Followers
144 Following
555 Posts
Posting my EE stuff here, mostly embedded and FPGA work.
Main accounthttps://dragon.style/@Tathar
Public Althttps://dragonchat.org/@Tathar
Tathar makes stuffFeb 23
Show threadBrycensRanchFeb 23

@GitHub

My account has been restored, thanks, GitHub!

https://cdn.discordapp.com/attachments/143867839282020352/1475501853180563579/image.png?ex=699db7af&is=699c662f&hm=55d7693691f0419641bd414655d6d220f47cf20f9d7d342cf41d0347a51a839b&

Tathar makes stuffFeb 23
BrycensRanchFeb 23
I’m sorry that I have to introduce myself this way to Mastodon. But @GitHub has shadow banned my GitHub account without any notification of enforcement. I’ve spent hundreds of hours on my software without pay. Now, it’s gone without a trace. My latest project, SnapX had 750+ stars and 650+ hours of my time. Now, others it’s like it was never there. The sad part is, GitHub was my project’s homepage. My project is suffering every minute this continues… https://cdn.discordapp.com/attachments/356003331962961920/1475471885746704504/XZZoFVZAni.png?ex=699d9bc6&is=699c4a46&hm=4329565a1dfe609f2c5a1332d4bf14d81bf38407e76af78c4543a6216aebd01d&
Tathar makes stuffFeb 14
deneb???Feb 14
printers are a kind of DAC
Show threadTathar makes stuffFeb 14
@jcm and this is how I realized I didn't have verilator installed
Show threadTathar makes stuffFeb 14

@jcm if you're looking for something to verify that your toolchain is working, they offer a hello world example

https://doc.veryl-lang.org/book/03_getting_started/02_hello_world.html

Veryl: A Modern Hardware Description Language

Veryl is a hardware description language which is designed as a SystemVerilog alternative.

Show threadTathar makes stuffFeb 14
@jcm You might be able to ask for one from https://github.com/veryl-lang/verylup or https://github.com/veryl-lang/veryl
GitHub - veryl-lang/verylup: Verylup: the Veryl toolchain installer

Verylup: the Veryl toolchain installer. Contribute to veryl-lang/verylup development by creating an account on GitHub.

GitHub
Show threadTathar makes stuffFeb 14
@jcm I don't think there's an official RISC-V build atm
Show threadTathar makes stuffFeb 14
@jcm You're installing on RISC-V?
Show threadTathar makes stuffFeb 14

@jcm I haven't used Veryl yet (just want to learn it) so my answers won't be as good as someone who actually used it. I'm relying heavily on https://doc.veryl-lang.org/book/01_introduction.html for now, but here's my best effort:

  • Veryl synthesizes to SV using veryl build

    • source: https://doc.veryl-lang.org/book/03_getting_started/02_hello_world.html#build-code

  • Veryl reads similarly to SV but with syntax that better conveys the intent, so it's probably better to look for those keywords, such as the special Veryl types clock and reset without logic

    • example: https://doc.veryl-lang.org/book/04_code_examples/01_module.html

    (click the play icon in the example to see the generated SV)

    SV can also be accessed from within Veryl through the use of the $sv namespace: https://doc.veryl-lang.org/book/05_language_reference/10_systemverilog_interoperation.html

  • I'll need some time to put one together. I can start working on it tonight.
    • Veryl: A Modern Hardware Description Language

    Veryl is a hardware description language which is designed as a SystemVerilog alternative.

    Tathar makes stuffFeb 14
    @jcm any chance of adding Veryl support?