Tathar makes stuffFeb 14
@jcm any chance of adding Veryl support?
Show threadJCM

Sure! But it would be nice if you could help me with a few things:

  • What is the simplest (= requiring the least commands and extra files) way to synthesize Veryl code into something that yosys can read (e.g. Verilog or SystemVerilog)?
  • How can I detect Veryl based on just the code (no file extensions)? Is there any particular line or string that every Veryl code (and generally no SystemVerilog code) contains?
  • Could you provide a simple example with exactly the same interface as the examples already present in the bot's profile description?
    • Feb 14 at 3:31pmWeb
    Show threadJCMFeb 14

    And it seems like I also need to figure out how to install Veryl in the first place:

    ╭─jcm💞cyndi@layla in ~ at 15:28:19 ╰─λ cargo install verylup ... ╭─jcm💞cyndi@layla in ~ at 15:45:26 took 13m56s ╰─λ verylup setup Error: unknown target :riscv64gc-unknown-linux-gnu
    Show threadTathar makes stuffFeb 14
    @jcm You're installing on RISC-V?
    Show threadJCMFeb 14
    Yeah, the server running the synthesis and everything is a Milk-V Mars.
    Milk-V

    Milk-V Mars is a high-performance RISC-V Single Board Computer (SBC) the size of a credit card, built on the StarFive JH7110. This four-core device supports a plug-and-play eMMC module, as well as up to 8GB of LPDDR4 memory. The board is equipped with three USB 3.0 ports, one USB 2.0 port, an HDMI 2.0 port that supports 4K resolution, an RJ45 Ethernet port that supports PoE (Power over Ethernet), and an M.2 E-Key slot for a WIFI/BT module. It also includes a 4-lane MIPI CSI and a 2-lane MIPI CSI, along with a 40-pin GPIO

    Show threadTathar makes stuffFeb 14
    @jcm I don't think there's an official RISC-V build atm
    Show threadJCMFeb 14
    Yeah, for most software there sadly isn't…
    But installing from source worked, it just took like 40 minutes 😅
    Show threadTathar makes stuffFeb 14

    @jcm if you're looking for something to verify that your toolchain is working, they offer a hello world example

    https://doc.veryl-lang.org/book/03_getting_started/02_hello_world.html

    Veryl: A Modern Hardware Description Language

    Veryl is a hardware description language which is designed as a SystemVerilog alternative.

    Show threadTathar makes stuffFeb 14
    @jcm and this is how I realized I didn't have verilator installed
    Show threadTathar makes stuffFeb 14
    @jcm You might be able to ask for one from https://github.com/veryl-lang/verylup or https://github.com/veryl-lang/veryl
    GitHub - veryl-lang/verylup: Verylup: the Veryl toolchain installer

    Verylup: the Veryl toolchain installer. Contribute to veryl-lang/verylup development by creating an account on GitHub.

    GitHub
    Show threadTathar makes stuffFeb 14

    @jcm I haven't used Veryl yet (just want to learn it) so my answers won't be as good as someone who actually used it. I'm relying heavily on https://doc.veryl-lang.org/book/01_introduction.html for now, but here's my best effort:

  • Veryl synthesizes to SV using veryl build

    • source: https://doc.veryl-lang.org/book/03_getting_started/02_hello_world.html#build-code

  • Veryl reads similarly to SV but with syntax that better conveys the intent, so it's probably better to look for those keywords, such as the special Veryl types clock and reset without logic

    • example: https://doc.veryl-lang.org/book/04_code_examples/01_module.html

    (click the play icon in the example to see the generated SV)

    SV can also be accessed from within Veryl through the use of the $sv namespace: https://doc.veryl-lang.org/book/05_language_reference/10_systemverilog_interoperation.html

  • I'll need some time to put one together. I can start working on it tonight.
    • Veryl: A Modern Hardware Description Language

    Veryl is a hardware description language which is designed as a SystemVerilog alternative.