Mastodawn

@jcm any chance of adding Veryl support?

Sure! But it would be nice if you could help me with a few things:

What is the simplest (= requiring the least commands and extra files) way to synthesize Veryl code into something that yosys can read (e.g. Verilog or SystemVerilog)?

How can I detect Veryl based on just the code (no file extensions)? Is there any particular line or string that every Veryl code (and generally no SystemVerilog code) contains?

Could you provide a simple example with exactly the same interface as the examples already present in the bot's profile description?

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Tathar makes stuff

@jcm I haven't used Veryl yet (just want to learn it) so my answers won't be as good as someone who actually used it. I'm relying heavily on https://doc.veryl-lang.org/book/01_introduction.html for now, but here's my best effort:

Veryl synthesizes to SV using veryl build

source: https://doc.veryl-lang.org/book/03_getting_started/02_hello_world.html#build-code

Veryl reads similarly to SV but with syntax that better conveys the intent, so it's probably better to look for those keywords, such as the special Veryl types clock and reset without logic

example: https://doc.veryl-lang.org/book/04_code_examples/01_module.html

(click the play icon in the example to see the generated SV)

SV can also be accessed from within Veryl through the use of the $sv namespace: https://doc.veryl-lang.org/book/05_language_reference/10_systemverilog_interoperation.html

I'll need some time to put one together. I can start working on it tonight.

Veryl: A Modern Hardware Description Language

Veryl is a hardware description language which is designed as a SystemVerilog alternative.