tnt4d ago

🎉 New video showing off running PCI express over COTS SFP modules and associated complications along with future plans.

And then a small side quest involving optical splitters and #ngscopeclient

https://youtu.be/XaDa9bBucEI

Definitely on the long side, sorry about that 😬 But I hope it's still interesting 🤞

Show threadMarcus Müller4d ago
@tnt oh yeah, that's cool.
Show threadMarcus Müller4d ago
@tnt surprised you can get away with just generating an independent clock device-side!
Show threadtnt

@funkylab Each serdes has some range it will lock in if close enough. When you think about it, 10G ethernet is also just data lane and a nominal rate.

And the "skip ordered set" are dummy data inserted periodically that can be added/removed as needed to keep in sync when crossing domains.

In Gen3 there is even something call SRIS "Separate Reference Independent Spread" where you can have independent SSC on each side. But seems specialized and couldn't get it to work so far. So no SSC for now.

Apr 7 at 8:57amWeb
Show threadMarcus Müller4d ago
@tnt ah I'm not surprised about the CDR working, I'm surprised that having a CDR that will be off from a reference clock makes it questionable why the 100 MHz clock was there in the first place? Is this just so that the PCIe cards in a system don't have to have their own reference oscillators to derive a nominal clock from? I feel I'm missing something here.
Show threadtnt4d ago

@funkylab Ah well as I noted in the video, if you have spread spectrum then using a separate 100 MHz doesn't "just work". So the reference provided by the main board follows the same spread spectrum. I think that was the main point of having it.

But saving the cards from having a 100 MHz ref might also have been a factor to allow dirt cheap boards.