tnt

🎉 New video showing off running PCI express over COTS SFP modules and associated complications along with future plans.

And then a small side quest involving optical splitters and #ngscopeclient

https://youtu.be/XaDa9bBucEI

Definitely on the long side, sorry about that 😬 But I hope it's still interesting 🤞

Apr 7 at 8:07amWeb
Show threadMarcus Müller4d ago
@tnt oh yeah, that's cool.
Show threadMarcus Müller4d ago
@tnt surprised you can get away with just generating an independent clock device-side!
Show threadtnt4d ago

@funkylab Each serdes has some range it will lock in if close enough. When you think about it, 10G ethernet is also just data lane and a nominal rate.

And the "skip ordered set" are dummy data inserted periodically that can be added/removed as needed to keep in sync when crossing domains.

In Gen3 there is even something call SRIS "Separate Reference Independent Spread" where you can have independent SSC on each side. But seems specialized and couldn't get it to work so far. So no SSC for now.

Show threadMarcus Müller4d ago
@tnt ah I'm not surprised about the CDR working, I'm surprised that having a CDR that will be off from a reference clock makes it questionable why the 100 MHz clock was there in the first place? Is this just so that the PCIe cards in a system don't have to have their own reference oscillators to derive a nominal clock from? I feel I'm missing something here.
Show threadtnt4d ago

@funkylab Ah well as I noted in the video, if you have spread spectrum then using a separate 100 MHz doesn't "just work". So the reference provided by the main board follows the same spread spectrum. I think that was the main point of having it.

But saving the cards from having a 100 MHz ref might also have been a factor to allow dirt cheap boards.

Show thread✧✦Catherine✦✧4d ago
@tnt oh, exciting!
Show threadGraham Sutherland / Polynomial4d ago

@tnt I just finished watching this - very very cool!

are you reasonably confident that the Alibaba accelerator cards will work for PCIe 3.0 capture? I'm considering pulling the trigger on one immediately 'cos having the capability to do bidirectional PCIe 3.0 capture would be extremely cool.

Show threadtnt4d ago

@gsuberland I'm still attempting to get a gen 3.0 link up and stable (without splitter). ATM I can get it up but AER reports many errors, although I suspect the issue is partly those cheap USB3 cable breakout. Will see how proper oculink works out.

Is there any reason you'd want to do the capture at gen3 rather than just forcing the target device to gen2 speed to make a capture ?

Show threadGraham Sutherland / Polynomial4d ago
@tnt good point, I suppose!
Show threadftg4d ago
@tnt
Nice video, thanks for making it!
And now I just need to avoid buying even more test equipment.
Show threadKeenan Tims2d ago
@tnt Neat! How does clocking work if you don't send the clock and don't do clock recovery? Is the refclk not actually used by the receiver?
Show threadtnt2d ago

@ktims I provide an independent 100 MHz reference on the other side of the link. See my answer to @funkylab in this thread
https://chaos.social/@tnt/116362590463613892

There will also be more details in upcoming video when I deal with Spread Spectrum.

tnt (@[email protected])

@[email protected] Each serdes has some range it will lock in if close enough. When you think about it, 10G ethernet is also just data lane and a nominal rate. And the "skip ordered set" are dummy data inserted periodically that can be added/removed as needed to keep in sync when crossing domains. In Gen3 there is even something call SRIS "Separate Reference Independent Spread" where you can have independent SSC on each side. But seems specialized and couldn't get it to work so far. So no SSC for now.

chaos.social