module my_code #(
parameter int WIDTH = 640,
parameter int HEIGHT = 480,
parameter int CONSOLE_COLUMNS = WIDTH / 8,
parameter int CONSOLE_ROWS = HEIGHT / 8
)(
input logic clk,
input logic rst,
input int px,
input int py,
input logic hsync,
input logic vsync,
input int col,
input int row,
output int char,
output logic [23:0] foreground_color,
output logic [23:0] background_color
);
logic [31:0] frame_counter = '0;
logic old_vsync = '0;
logic [7:0] red, green, blue;
// Define a simple character set - ASCII for demonstration. Can be expanded.
logic [7:0] char_code;
localparam MAX_CHARS = 256; //ASCII range
always_comb begin
// Simple character mapping based on row and column. Makes it look like text!
if (row < CONSOLE_ROWS && col < CONSOLE_COLUMNS) begin
char_code = { (col % MAX_CHARS), (row % MAX_CHARS) }; //Basic char selection.
//This is a simplistic demo, a real console would need more sophisticated mapping!
end else begin
char_code = 8'h20; // Space if out of bounds
end
red = 8'(col * 4);
green = 8'(py);
blue = frame_counter[7:0];
background_color = {red, green, blue};
//Foreground color - a simple gradient based on row.
//This adds visual interest and makes it look like something is "drawing."
foreground_color = {
(row % 16'hF000) , // Red component: Gradual change in red
(row % 16'h00FF), // Green component: Gradual change in green
(row % 16'h0000) // Blue Component: Constant blue.
};
char = char_code;
end
always_ff @(posedge clk) begin
if (vsync == 1'b0 && old_vsync == 1'b1) begin
frame_counter <= frame_counter + 1;
end
old_vsync <= vsync;
end
endmodule
TimingClockAchievedConstraint
Code
#FPGA #Icepi-Zero #HDL #SystemVerilog
Sucess!
UtilizationCellUsedAvailableUsageDCCA2563.6%
EHXPLLL1250%
TRELLIS_COMB819242883.4%
TRELLIS_FF142242880.6%
TRELLIS_IO101975.1%
TimingClockAchievedConstraint
$glbnet$clkp41.45 MHz25 MHz
$glbnet$clkt361.01 MHz250 MHz
Code
module my_code #(
parameter int WIDTH = 640,
parameter int HEIGHT = 480,
parameter int CONSOLE_COLUMNS = WIDTH / 8,
parameter int CONSOLE_ROWS = HEIGHT / 8
)(
input logic clk,
input logic rst,
input int px,
input int py,
input logic hsync,
input logic vsync,
input int col,
input int row,
output int char,
output logic [23:0] foreground_color,
output logic [23:0] background_color
);
logic [31:0] frame_counter = '0;
logic old_vsync = '0;
logic [7:0] red, green, blue;
// Define a simple character set - ASCII for demonstration. Can be expanded.
logic [7:0] char_code;
localparam MAX_CHARS = 256; //ASCII range
always_comb begin
// Simple character mapping based on row and column. Makes it look like text!
if (row < CONSOLE_ROWS && col < CONSOLE_COLUMNS) begin
char_code = { (col % MAX_CHARS), (row % MAX_CHARS) }; //Basic char selection.
//This is a simplistic demo, a real console would need more sophisticated mapping!
end else begin
char_code = 8'h20; // Space if out of bounds
end
red = 8'(col * 4);
green = 8'(py);
blue = frame_counter[7:0];
background_color = {red, green, blue};
//Foreground color - a simple gradient based on row.
//This adds visual interest and makes it look like something is "drawing."
foreground_color = {
(row % 16'hF000) , // Red component: Gradual change in red
(row % 16'h00FF), // Green component: Gradual change in green
(row % 16'h0000) // Blue Component: Constant blue.
};
char = char_code;
end
always_ff @(posedge clk) begin
if (vsync == 1'b0 && old_vsync == 1'b1) begin
frame_counter <= frame_counter + 1;
end
old_vsync <= vsync;
end
endmodule
#FPGA #Icepi-Zero #HDL #SystemVerilog