Ryan Castellucci (they/them) 
Saw a blog post titled "How many registers does an x86-64 CPU have?" and my immediate thought was "it's impossible to know and a sin to ask".
If you think the answer is 16, by the way, no it is not.
Clara
dmi 💽 @ryanc grins heavily with what extensions, may I ask? x86-64 is such a wide selector that I could only provide a rough range! 
@domi the finest artisanal model specific registers
jn (BE side)
Graham Sutherland / Polynomial@ryanc yeah uhhh off the top of my head
rax, rbx, rcx, rdx, r8-r15, rdi, rsi, rsp, rbp, rip and all the components thereof, and rflags
zmm0-zmm??? (can't remember how many we have now) plus the ymm/xmm components.
6 ye olde segment registers.
gdtr, ldtr, idtr, and another I forgot the name of.
maybe 5 control registers? they're numbered to 15 but most are reserved
8 debug registers
x87 FPU and MMX weirdness
hundreds of MSRs, hundreds more if you count CPUID leaves
plus internal regs
AMS@gsuberland @ryanc And however many delay slots worth of them due to microcode shenanigans, and the debug registers (you can use them to store keymat if coldboot and DMA attacks are in your threatmodel).
@ryanc based on the reverse engineered microcode from Intel platforms we have RED unlock on I'd guess there are probably a hundred named internal microarchitectural registers at least (if we count unnamed we'll be here all week)
@ryanc and that's if you only count the internal registers for the main x86-64 cores and the surrounding cache/memory architecture.
if we include internal registers for UPI, PCIe, integrated graphics, TPM, IOMMU, VT-d/VT-x, and features like AMT and VROC, there's thousands of them.
Nspace@gsuberland @ryanc we have microcode for amd too :p and it works on the newest cpus unlike on intel. there are a lot of internal registes you can access only through microcode
pixx@pixx @gsuberland @ryanc
https://youtu.be/sUFDKTaCQEk
https://bughunters.google.com/blog/zen-and-the-art-of-microcode-hacking
https://youtu.be/sUFDKTaCQEk
https://bughunters.google.com/blog/zen-and-the-art-of-microcode-hacking
OffensiveCon25 - Matteo Rizzo, Kristoffer `spq` Janke, Eduardo Vela Nava and Josh Eads
EndlessMason
artemist@gsuberland @ryanc avx512 also comes with the k1-k7 opmask registers
Tom Forsyth@artemist @gsuberland @ryanc I can personally assure you that k0 is a very real and existing register.
@TomF @gsuberland @ryanc i thought k0 was one of those "hardwired to 0" registers, but i might be thinking of riscv
@gsuberland @artemist @ryanc It would have been elegant architecture to use the GPRs, but physically it would have been a bad idea - the two live in very different parts of the chip. I talk about it in my video:
https://vimeo.com/450406346
k0 is a perfectly normal register. The only special thing is that for vector instructions, that ENCODING is used to mean "no mask". This is similar to how SP/BP/R12/R13 encodings meaning special things in MOD-R/M - the registers themselves aren't special.
Tom Forsyth - The Lifecycle of an Instruction Set
Handmade Seattle 2019
iximeow@gsuberland @artemist @ryanc It was very annoying to have to invent a whole new register file and mini-ISA, but the designers would have chased me with flaming torches and pitchforks if I'd tried to make them do it with GPRs.
@gsuberland @artemist @ryanc "Designer" has a very specific meaning in Intel jargon - those are the people doing low-level layout & timing.
@gsuberland @artemist @ryanc Morbid interest I wondered if Google's AI got this rather esoteric question right. It actually did! Almost. It fell over right at the end on this, which is amusingly "not-even-wrong":
@gsuberland @artemist @ryanc So the first part is not correct - k0 does NOT return all-1s.
But it is correct that "kxnorw k1, k0, k0 sets k1 to all ones"! Because so does "kxnorw k1, k5, k5" <facepalm>
Cat 🐈🥗 (D.Burch) 
@ryanc Oh, that's easy!
x86-64
x86 = 64
x = 64⁄86
x = 32⁄43
So it has at least 1.344 registers!
@catsalad your logic is flawless
Klaus Frank
Gerard
Andrew Zonenberg@ryanc There's not even 16-visible ISA registers.
If you *really* want to know how many uarch registers there are, I guess you can start by decapping the chip and counting DFF cells and SRAM bits :P That will at least give a hard upper bound
Javier@ryanc
Long ago, I was starting to understand register renaming (the phrase "register file" gave me existencial doubts), and then they came with hyperthreading...
Now I feel CPU architecture is purely a spectator sport.
Long ago, I was starting to understand register renaming (the phrase "register file" gave me existencial doubts), and then they came with hyperthreading...
Now I feel CPU architecture is purely a spectator sport.
rj
Jeff@javierg @ryanc an ISA is best understood as a defined interface that allow the engineers working on compilers and operating systems to reason about the hardware without going insane and allows the electrical engineers to go crazy while having something to conform to so they don't break everything all of the time.
Olivia
HP van Braam@ryanc between 40 and transistor count / 3.
That's accurate, but not very precise. 😀
Marcella Francesca 
A whole bunch of registers. If you run out of it, You might considder to stop using Macro Assembler and write GWBasic programs...
RAX, RBX, RCX, RDX, EAX, EBX, ECX, EDX, RDI, RSI, RBP, RSP, EDI, ESI, EBP, ESP, R8-R15, CS, DS, ES, FS, GS, SS, RIP, EIP, RFLAGS, EFLAGS, CR0-CR4, DR0-DR7, MSRs, SIMD, XMM0-XMM15, YMM0-YMM15, ZMM0-ZMM31, MM0--MM7, ST0-ST7, MXCSR.
I hope I copied all...
Peter Bindels@ryanc @bitchboss you forgot ah, al, ch, cl, dh, dl, bh, bl, dil, sil, spl and bpl. And of course r8l, r8w etc.
@bitchboss @ryanc @gsuberland we even got low ones for di, si, bp and sp... which means you cannot mov ah, bpl...
Tim Ward ⭐🇪🇺🔶 #FBPE@ryanc Even for a Z80 it's not a trivial answer. (Yes I do know someone who wrote some code that used the R register.)
lp0 on fire 
@TimWardCam @ryanc, let's see… from what I remember:
8-bit registers (treatable as 16-bit pairs): A, F, B, C, D, E, H, L.
16-bit registers (treatable as 8-bit halves): IX, IY.
8-bit registers: I, R.
16-bit registers: AF', BC', DE', HL', SP, PC.
18 registers in total. I'm specifically not counting different views as distinct registers: AF is counted as A and F, but IXH and IXL are counted as IX.
Yes, some aspects of this are… somewhat arbitrary. I could count BC, DE and HL as three rather than six and it wouldn't be wrong. I could count AF that way too – and it probably does match the other pairs in terms of the actual hardware design (and it could reasonably be called FA as, looking at the opcode patterns, it makes sense for A to be the lower 8 bits).
Now. Have I missed anything…?
@lp0_on_fire @ryanc Most people never come across R. I knew someone who bult a Rugby clock with no RAM, using just the registers as memory, and to find enough space they needed to use the top few bits of the R register (the bottom few bits cycled too fast to be useful).
@TimWardCam @ryanc IIRC, the ZX Spectrum relied on the R register for correct screen display? I'd need to recheck the book.
halcy 
Maria “indigoviolet” Ivy@ryanc (xkcd 2867)
Kaye
gunstick
keinna
Cassandrich@ryanc It depends a lot on what you mean by registers and which execution domain you're talking about.
Patrick Morris Miller@ryanc Related: I grew up thinking the 6502 had three registers.
Then I saw someone say X and Y weren't registers at all.
Then I saw someone else say the first 256 bytes of RAM *were* registers.
Very Human Robot@ryanc
You *can* talk about "architectural registers" though. But even there, there are a bunch of special purpose registers, so what counts as a "register?"
You *can* talk about "architectural registers" though. But even there, there are a bunch of special purpose registers, so what counts as a "register?"
Andre