It seems hard to estimate, but it feels like a number with way too many zeros after it.
@david_chisnall @sophieschmieg I don't believe there is any benefit of hardware offload for PQC.
PQC is only used for key agreement or signature, which is a very small part of a TLS flow. Encryption is still going to stay AES or Chacha.
I believe this was meant for the amount of (human) work required to prototype, collaborate, specify, certify and deploy.
To be honest, the most problematic portion at the moment is the lack of support for secure storage (HSMs, TPMs, yubikeys, ...) of PQC private keys. And this won't happen for a little while.
@sophieschmieg @david_chisnall I mainly work around code-signing use-cases. The larger signatures are definitely hard to retrofit in existing systems.
This is a major engineering cost for us.
@sophieschmieg @david_chisnall That and CPU vendors doing their own thing because why not.
Out of every solutions out there, they made an effort in picking the worst one.
@baloo @david_chisnall @vathpela but, but, but code signing is supposed to be the easy part 🫠. No seriously, compared to identity and pki, code signing has so much fewer constraints.
I guess other than firmware signing, that is also really hard.
@sophieschmieg @david_chisnall @vathpela I don’t know. You still need key delegation and revocation to do it proper. Either fully custom or an x509 pki. There are less constraints than webpki for sure, but still doesn’t feel quite easy.
I can’t wait for the dnssec folks to chime in. This is going to be so much fun over there!
@sophieschmieg @baloo @vathpela
I’m mostly interacting with this stuff from an embedded perspective. We’re looking at using ML-DSA for code signing. The RAM requirements are quite high and the signing takes longer than the hashing, but it’s still only on the order of a few million cycles, so completely fine if you build a secure update flow rather than a secure boot one. We’re mostly wondering if we can get away with just the post-quantum schemes, because the code size of having to do both is annoying.
FIPS205 looks incredibly hard to run on embedded devices at all, let alone without side channels. We’ll see how that goes.
EDIT: To slightly return to my original point, if FIPS205 makes hardware floating point (especially constant power-and-time hardware floating point) a table stakes feature for microcontrollers, this may end up being a net positive overall.