big awoo notationI want to see if the thoughts of others align with mine.
An FPGA toolchain should optimise for:
An FPGA toolchain should optimise for:
highest worst-case Fmax
highest average Fmax
highest best-case Fmax
Poll ended at .
Luke Wren@lofty Depends how many parallel jobs I am allowed to submit to get that golden seed 😅
@wren6991 I'm computing distributions of 100 runs, so
@lofty If I'm comparing RTL changes for fmax then I'll usually do ~100 runs and take the median. Seems reasonable because 8 runs aiming for median frequency should have only a 0.4% chance of all failing. Most client machines have 8 parallel threads of execution available these days.
I don't particularly care about the mean because if I get a worst-case result then you can bet I'm re-rolling, so the tail values don't matter.
I don't think it's *good* that seed sweeping is the optimal way of using the tools, but the fact is it reduces variance as well as increasing expected fmax.
@lofty Also bear in mind my comparison point here is Vivado which has a >> 0.4% chance of just segfaulting for no apparent reason, so I find that kind of probability acceptable
mei@wren6991 @lofty one trick i've seen for dealing with fpga toolchains that i really like is to LD_PRELOAD this bad boy. makes them much less flakey.
Andrew Zonenberg
the vessel of morganna@azonenberg @mei @lofty @wren6991 this sort of software bodge is literally built into the Windows compatibility shim and applied for a metric crapload of programs. we certainly live in times
@azonenberg @mei @lofty @wren6991 yep, oversized allocations and time-delayed free. the name "enterprise-malloc" is so incredibly accurate it hurts. the windows compat shim often gets tuned to limit the over-allocation size since it's a per-program profile, so it's not as noticeable
@astraleureka @mei @lofty @wren6991 the only thing worse than this shitpost is it not being a shitpost