I'm super happy that my latest chip Greyhound has been accepted for production! 🥳
It was designed with open source EDA tools and the IHP Open Source PDK.
Find out more here: https://github.com/mole99/greyhound-ihp
And down below ⬇️
I'm super happy that my latest chip Greyhound has been accepted for production! 🥳
It was designed with open source EDA tools and the IHP Open Source PDK.
Find out more here: https://github.com/mole99/greyhound-ihp
And down below ⬇️
🧠 So what does it do? It is part RISC-V SoC and part eFPGA.
At its heart is the CV32E40X from the OpenHW group (https://github.com/openhwgroup/cv32e40x) and an FPGA fabric generated using the FABulous framework (https://github.com/FPGA-Research/FABulous).
While the SoC is fairly basic with a QSPI Flash and PSRAM controller, 8kB of SRAM and a UART, more functionality can be implemented using the embedded FPGA.
The FPGA itself is relatively small (less than 1k LUT4) but has some nice primitives such as SRAM, MAC and dedicated register files. Greyhound's embedded FPGA can be used as a custom instruction extension, as a peripheral or as a completely standalone FPGA with 32 I/Os.
- Missing a peripheral? Simply implement it with the eFPGA.
- Want to speed up code execution? Write your own custom instruction extension.
And best of all: You can generate the FPGA bitstream using upstream yosys and nextpnr.
@mole99 This is something I hope future microcontrollers do... allocate a bit of fabric to custom peripherals so that you can add your own.
Beagle PRUs, RP2040 PIOs, and "that STM32 feature that exposes a parallel bus externally whose name I forget" are halfway there :D.