mole99I'm super happy that my latest chip Greyhound has been accepted for production! 🥳
It was designed with open source EDA tools and the IHP Open Source PDK.
Find out more here: https://github.com/mole99/greyhound-ihp
And down below ⬇️
🧠 So what does it do? It is part RISC-V SoC and part eFPGA.
At its heart is the CV32E40X from the OpenHW group (https://github.com/openhwgroup/cv32e40x) and an FPGA fabric generated using the FABulous framework (https://github.com/FPGA-Research/FABulous).
While the SoC is fairly basic with a QSPI Flash and PSRAM controller, 8kB of SRAM and a UART, more functionality can be implemented using the embedded FPGA.
The FPGA itself is relatively small (less than 1k LUT4) but has some nice primitives such as SRAM, MAC and dedicated register files. Greyhound's embedded FPGA can be used as a custom instruction extension, as a peripheral or as a completely standalone FPGA with 32 I/Os.
- Missing a peripheral? Simply implement it with the eFPGA.
- Want to speed up code execution? Write your own custom instruction extension.
And best of all: You can generate the FPGA bitstream using upstream yosys and nextpnr.
I'm really glad that I completed this project as part of my Master's thesis.
This wouldn't have been possible without the open source community providing IPs and frameworks to build on. I'm also grateful to IHP GmbH and the publicly funded IHP-Open-DesignLib that enabled the tapeout of this chip.
- IHP Open Source PDK: https://github.com/IHP-GmbH/IHP-Open-PDK
- IHP-Open-DesignLib: https://ihp-open-ip.readthedocs.io/en/latest/
If you have any questions about Greyhound or about open source chip design in general, feel free to ask!
William D. Jones@mole99 This is something I hope future microcontrollers do... allocate a bit of fabric to custom peripherals so that you can add your own.
Beagle PRUs, RP2040 PIOs, and "that STM32 feature that exposes a parallel bus externally whose name I forget" are halfway there :D.
@cr1901 Yeah, I do too. But if they add an eFPGA, it better be programmable with open source tools 😄
jn (big endian energy)
Kelly MacNeill@mole99 what’s the max frequency?
@pyromuffin Depends on the conditions 😉
- nom_fast_1p32V_m40C: 85 MHz
- nom_typ_1p20V_25C: 55 MHz
- nom_slow_1p08V_125C: 34 MHz
This is for the SoC, the max frequency for the FPGA depends of course on your design.
Note that this is on a 130nm process.
@mole99 ah, thanks for the info!
crzwdjk ✅ @mole99 Oh this thing looks cool, and would be perfect for the project I was working on, which requires a bit of compute and a bit of fast, custom I/O. I was trying to make an FPGA-based dumb terminal, so the parts that outputs the video signal and read a PS/2 keyboard could live in the FPGA and the logic for handling the escape codes and stuff would run on the CPU.
@crzwdjk That would be cool indeed! Unfortunately, I won't be able to give away or sell Greyhound, as the tapeout is funded with public money. But as soon as I get it back (and it works 🤞), I'll definitely try something similar 😃
Greg@mole99 this is awesome!! 🤩🙌
@gregdavill Thanks so much! Glad you like it 😊️