noahjunior10Nov 29, 2024
FCLC

Hey friends!
For folks interested in #RISCV, and especially #RVV, here's some information on the #tenstorrent in house designed CPU!

High level, vector is 2x256, full RVV1.0 as well as a fair few of the optional extras to RVV1.0!

Phoronix article here: https://www.phoronix.com/news/LLVM-20-Tenstorrent-Ascalon

LLVM patches here: https://github.com/llvm/llvm-project/pull/115100

One Pager: https://cdn.sanity.io/files/jpb4ed5r/production/6a28f7d59b6d1300fccdbdd394e192a4fd5f54c6.pdf

#HPC #SIMD

LLVM Merges Support The For Tenstorrent TT-Ascalon-D8 RISC-V CPU

Adding to the interesting code building up for next spring's release of the LLVM 20 compiler stack is having the Tenstorrent TT-Ascalon D8 as the newest RISC-V processor target.

Nov 28, 2024 at 4:30pmWeb
Show threadcamelcdrNov 28, 2024

@fclc

> Scheduling model will be added in a separate PR

need

Show threadFCLCNov 28, 2024
@camelcdr 🔜 ™️
Show threadAlan SillNov 28, 2024
@fclc Is it available in a SBC or test board suitable for dropping into the hands of students?
Show threadFCLCNov 28, 2024

@AlanSill Ascalon is going through software enablement, and won’t be available for {a while}

There’s a part coming out {soon} that may be able to help with RISCV enablement for students

Show threadcamelcdrNov 28, 2024

@fclc @AlanSill My guess from previous TT publications:

Either Black Hole, which has X280s or maybe something like a standalone bobcat+.

Show threadFCLCNov 29, 2024
@camelcdr @AlanSill 🤐