Thibaut JacqminMay 9, 2025

πŸš€ Pushing the limits of superinductors with vertically‑stacked Josephson junctions

πŸ”Check our new designs of high-impedance hyper-inductors. We open a scalable path to high impedance hyperinductors for exotic protected qubits:

https://arxiv.org/abs/2505.02764

πŸ“„A related design has been proposed recently in the group of Alexey Ustinov (ArXiv:2503.11437v1).

#Quantum #Superinductor #JosephsonJunctions #Nanofab #QuantumHardware

LKB - CEA - LPENS - Alice & Bob

Hyperinductance based on stacked Josephson junctions

Superinductances are superconducting circuit elements that combine a large inductance with a low parasitic capacitance to ground, resulting in a characteristic impedance exceeding the resistance quantum $R_Q = h/(2e)^2 \simeq 6.45 \mathrm{k}Ξ©$. In recent years, these components have become key enablers for emerging quantum circuit architectures. However, achieving high characteristic impedance while maintaining scalability and fabrication robustness remains a major challenge. In this work, we present two fabrication techniques for realizing superinductances based on vertically stacked Josephson junctions. Using a multi-angle Manhattan (MAM) process and a zero-angle (ZA) evaporation technique -- in which junction stacks are connected pairwise using airbridges -- we fabricate one-dimensional chains of stacks that act as high-impedance superconducting transmission lines. Two-tone microwave spectroscopy reveals the expected $\sqrt{n}$ scaling of the impedance with the number of junctions per stack. The chain fabricated using the ZA process, with nine junctions per stack, achieves a characteristic impedance of $\sim 16 \mathrm{k}Ξ©$, a total inductance of $5.9 \mathrm{ΞΌH}$, and a maximum frequency-dependent impedance of $50 \mathrm{k}Ξ©$ at 1.4 GHz. Our results establish junction stacking as a scalable, robust, and flexible platform for next-generation quantum circuits requiring ultra-high impedance environments.

arXiv.org
cynicalsecurity Dec 18, 2022

[This article is somewhat outside the range of what I normally look at but my father taught me about Josephson Junctions back in the 1980s and they sort of "stuck", besides superconducting electronics has been a holy grail in forever. See this a bit in the light of the recent fusion announcement and file under "cool science".]

J. Volk et al., "Low-Cost Superconducting Fan-Out with Repurposed Josephson Junctions"ΒΉ

Superconductor electronics (SCE) promise computer systems with orders of magnitude higher speeds and lower energy consumption than their complementary metal-oxide semiconductor (CMOS) counterpart. At the same time, the scalability and resource utilization of superconducting systems are major concerns. Some of these concerns come from device-level challenges and the gap between SCE and CMOS technology nodes, and others come from the way Josephson Junctions (JJs) are used. Towards this end, we notice that a considerable fraction of hardware resources are not involved in logic operations, but rather are used for fan-out and buffering purposes. In this paper, we ask if there is a way to reduce these overheads; propose the repurposing of JJs at the cell boundaries for fan-out; and establish a set of rules to discretize critical currents in a way that is conducive to this reassignment. Finally, we demonstrate the accomplished gains through detailed analog simulations and modeling analyses. Our experiments indicate that the introduced method leads to a 48% savings in the JJ count in a tree with a fan-out of 1024, as well as an average of 43% of the JJ count for signal splitting and 32% for clock fan-out in ISCAS'85 benchmarks.

#HPC #Supercomputers #Supercondictivity #JosephsonJunctions

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ΒΉ https://arxiv.org/abs/2206.07817

Low-Cost Superconducting Fan-Out with Repurposed Josephson Junctions

Superconductor electronics (SCE) promise computer systems with orders of magnitude higher speeds and lower energy consumption than their complementary metal-oxide semiconductor (CMOS) counterpart. At the same time, the scalability and resource utilization of superconducting systems are major concerns. Some of these concerns come from device-level challenges and the gap between SCE and CMOS technology nodes, and others come from the way Josephson Junctions (JJs) are used. Towards this end, we notice that a considerable fraction of hardware resources are not involved in logic operations, but rather are used for fan-out and buffering purposes. In this paper, we ask if there is a way to reduce these overheads; propose the repurposing of JJs at the cell boundaries for fan-out; and establish a set of rules to discretize critical currents in a way that is conducive to this reassignment. Finally, we demonstrate the accomplished gains through detailed analog simulations and modeling analyses. Our experiments indicate that the introduced method leads to a 48% savings in the JJ count in a tree with a fan-out of 1024, as well as an average of 43% of the JJ count for signal splitting and 32% for clock fan-out in ISCAS'85 benchmarks.

arXiv.org